/* ###################### CMSIS Support for Cortex-M4/7/33/35P/55 SIMD Instructions ####################### */ /** \defgroup intrinsic_SIMD_gr Intrinsic Functions for SIMD Instructions \brief Access to dedicated SIMD instructions available on Armv7E-M (Cortex-M4/M7), Armv8-M Mainline (Cortex-M33/M35P), and Armv8.1-M (Cortex-M55/M85). \details <b>Single Instruction Multiple Data (SIMD)</b> extensions are provided <b>only for Cortex-M4 and Cortex-M7 cores</b> to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used. <b>SIMD Features:</b> - Simultaneous computation of 2x16-bit or 4x8-bit operands - Fractional arithmetic - User definable saturation modes (arbitrary word-width) - Dual 16x16 multiply-add/subtract 32x32 fractional MAC - Simultaneous 8/16-bit select operations - Performance up to 3.2 GOPS at 800MHz - Performance is achieved with a "near zero" increase in power consumption on a typical implementation \b Examples: \b Addition: Add two values using SIMD function \code uint32_t add_halfwords(uint32_t val1, uint32_t val2) { return __SADD16(val1, val2); } \endcode \b Subtraction: Subtract two values using SIMD function \code uint32_t sub_halfwords(uint32_t val1, uint32_t val2) { return __SSUB16(val1, val2); } \endcode \b Multiplication: Performing a multiplication using SIMD function \code uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2) { return __SMUAD(val1, val2); } \endcode @{ */ /**************************************************************************************************/ /** \brief GE setting quad 8-bit signed addition \details This function performs four 8-bit signed integer additions. The GE bits of the APSR are set according to the results of the additions. \param val1 first four 8-bit summands. \param val2 second four 8-bit summands. \returns \li the addition of the first bytes from each operand, in the first byte of the return value. \li the addition of the second bytes of each operand, in the second byte of the return value. \li the addition of the third bytes of each operand, in the third byte of the return value. \li the addition of the fourth bytes of each operand, in the fourth byte of the return value. \par Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. \par If \em res is the return value, then: \li if res[7:0] \>= 0 then APSR.GE[0] = 1 else 0 \li if res[15:8] \>= 0 then APSR.GE[1] = 1 else 0 \li if res[23:16] \>= 0 then APSR.GE[2] = 1 else 0 \li if res[31:24] \>= 0 then APSR.GE[3] = 1 else 0 \par Operation: \code res[7:0] = val1[7:0] + val2[7:0] res[15:8] = val1[15:8] + val2[15:8] res[23:16] = val1[23:16] + val2[23:16] res[31:24] = val1[31:24] + val2[31:24] \endcode */ uint32_t __SADD8(uint32_t val1, uint32_t val2); /**************************************************************************************************/ /** \ingroup Intrinsic_SIMD_gr \brief Q setting quad 8-bit saturating addition \details This function enables you to perform four 8-bit integer additions, saturating the results to the 8-bit signed integer range -2<sup>7</sup> \<= x \<= 2<sup>7</sup> - 1. \param val1 first four 8-bit summands. \param val2 second four 8-bit summands. \returns \li the saturated addition of the first byte of each operand in the first byte of the return value. \li the saturated addition of the second byte of each operand in the second byte of the return value. \li the saturated addition of the third byte of each operand in the third byte of the return value. \li the saturated addition of the fourth byte of each operand in the fourth byte of the return value. \par The returned results are saturated to the 16-bit signed integer range -2<sup>7</sup> \<= x \<= 2<sup>7</sup> - 1. \par Operation: \code res[7:0] = val1[7:0] + val2[7:0] res[15:8] = val1[15:8] + val2[15:8] res[23:16] = val1[23:16] + val2[23:16] res[31:24] = val1[31:24] + val2[31:24] \endcode */ uint32_t __QADD8(uint32_t val1, uint32_t val2); /**************************************************************************************************/ /** \brief Quad 8-bit signed addition with halved results \details This function enables you to perform four signed 8-bit integer additions, halving the results. \param val1 first four 8-bit summands. \param val2 second four 8-bit summands. \returns \li the halved addition of the first bytes from each operand, in the first byte of the return value. \li the halved addition of the second bytes from each operand, in the second byte of the return value. \li the halved addition of the third bytes from each operand, in the third byte of the return value. \li the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. \par Operation: \code res[7:0] = val1[7:0] + val2[7:0] >> 1 res[15:8] = val1[15:8] + val2[15:8] >> 1 res[23:16] = val1[23:16] + val2[23:16] >> 1 res[31:24] = val1[31:24] + val2[31:24] >> 1 \endcode */ uint32_t __SHADD8(uint32_t val1, uint32_t val2); /**************************************************************************************************/ /** \ingroup Intrinsic_SIMD_gr \brief GE setting quad 8-bit unsigned addition \details This function enables you to perform four unsigned 8-bit integer additions. The GE bits of the APSR are set according to the results. \param val1 first four 8-bit summands for each addition. \param val2 second four 8-bit summands for each addition. \returns \li the halved addition of the first bytes from each operand, in the first byte of the return value. \li the halved addition of the second bytes from each operand, in the second byte of the return value. \li the halved addition of the third bytes from each operand, in the third byte of the return value. \li the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. \par Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. \par If \em res is the return value, then: \li if res[7:0] \>= 0x100 then APSR.GE[0] = 1 else 0 \li if res[15:8] \>= 0x100 then APSR.GE[1] = 1 else 0 \li if res[23:16] \>= 0x100 then APSR.GE[2] = 1 else 0 \li if res[31:24] \>= 0x100 then APSR.GE[3] = 1 else 0 \par Operation: \code res[7:0] = val1[7:0] + val2[7:0] res[15:8] = val1[15:8] + val2[15:8] res[23:16] = val1[23:16] + val2[23:16] res[31:24] = val1[31:24] + val2[31:24] \endcode */ uint32_t __UADD8(uint32_t val1, uint32_t val2); /**************************************************************************************************/ /** \brief Quad 8-bit unsigned saturating addition \details This function enables you to perform four unsigned 8-bit integer additions, saturating the results to the 8-bit unsigned integer range 0 \< x \< 2<sup>8</sup> - 1. \param val1 first four 8-bit summands. \param val2 second four 8-bit summands. \returns \li the halved addition of the first bytes in each operand, in the first byte of the return value. \li the halved addition of the second bytes in each operand, in the second byte of the return value. \li the halved addition of the third bytes in each operand, in the third byte of the return value. \li the halved addition of the fourth bytes in each operand, in the fourth byte of the return value. \par The results are saturated to the 8-bit unsigned integer range 0 \< x \< 2<sup>8</sup> - 1. \par Operation: \code res[7:0] = val1[7:0] + val2[7:0] res[15:8] = val1[15:8] + val2[15:8] res[23:16] = val1[23:16] + val2[23:16] res[31:24] = val1[31:24] + val2[31:24] \endcode */ uint32_t __UQADD8(uint32_t val1, uint32_t val2); /**************************************************************************************************/ /** \brief Quad 8-bit unsigned addition with halved results \details This function enables you to perform four unsigned 8-bit integer additions, halving the results. \param val1 first four 8-bit summands. \param val2 second four 8-bit summands. \returns \li the halved addition of the first bytes in each operand, in the first byte of the return value. \li the halved addition of the second bytes in each operand, in the second byte of the return value. \li the halved addition of the third bytes in each operand, in the third byte of the return value. \li the halved addition of the fourth bytes in each operand, in the fourth byte of the return value. \par Operation: ...
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