/**************************************************************************************************/ /** \defgroup Core_Register_gr Core Register Access \brief Functions to access the Cortex-M core registers. \details The following functions provide access to Cortex-M core registers. @{ */ /**************************************************************************************************/ /** \brief Read the CONTROL register \details The function reads the CONTROL register value using the instruction \b MRS. \n\n The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits: \n - \b CONTROL[2] [only Cortex-M4 and Cortex-M7] - =0 FPU not active - =1 FPU active \n\n - \b CONTROL[1] - =0 In handler mode - MSP is selected. No alternate stack possible for handler mode. - =0 In thread mode - Default stack pointer MSP is used. - =1 In thread mode - Alternate stack pointer PSP is used. \n\n - \b CONTROL[0] [not Cortex-M0] - =0 In thread mode and privileged state. - =1 In thread mode and user state. \returns CONTROL register value \remarks - The processor can be in user state or privileged state when running in thread mode. - Exception handlers always run in privileged state. - On reset, the processor is in thread mode with privileged access rights. \sa - \ref __set_CONTROL; CONTROL_Type - \ref ref_man_sec */ uint32_t __get_CONTROL(void); /**************************************************************************************************/ /** \brief Set the CONTROL Register \details The function sets the CONTROL register value using the instruction \b MSR. \n\n The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits: \n - \b CONTROL[2] [only Cortex-M4 and Cortex-M7] - =0 FPU not active - =1 FPU active \n\n - \b CONTROL[1] - Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0). - =0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode. - =0 In thread mode - Default stack pointer MSP is used. - =1 In thread mode - Alternate stack pointer PSP is used. \n\n - \b CONTROL[0] [not writeable for Cortex-M0] - Writeable only when the processor is in privileged state. - Can be used to switch the processor to user state (thread mode). - Once in user state, trigger an interrupt and change the state to privileged in the exception handler (the only way). - =0 In thread mode and privileged state. - =1 In thread mode and user state. \param [in] control CONTROL register value to set \remarks - The processor can be in user state or privileged state when running in thread mode. - Exception handlers always run in privileged state. - On reset, the processor is in thread mode with privileged access rights. \sa - \ref __get_CONTROL; __set_PSP; __set_MSP; CONTROL_Type - \ref ref_man_sec */ void __set_CONTROL(uint32_t control); /**************************************************************************************************/ /** \brief Read the IPSR register \details The function reads the Interrupt Program Status Register (IPSR) using the instruction \b MRS. \n\n The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). Each exception has an associated unique IRQn number. The following bits are used: - \b ISR_NUMBER (IPSR[8:0]) - = 0 Thread mode - = 1 Reserved - = 2 NMI - = 3 HardFault - = 4 MemManage - = 5 BusFault - = 6 UsageFault - = 7 SecureFault - = 8-10 Reserved - = 11 SVC - = 12 Reserved for Debug - = 13 Reserved - = 14 PendSV - = 15 SysTick - = 16 IRQ0 - ... - = n+15 IRQ(n-1) \returns ISPR register value \remarks - This register is read-only. \sa - \ref __get_xPSR; IPSR_Type - \ref NVIC_gr - \ref ref_man_sec */ uint32_t __get_IPSR(void); /**************************************************************************************************/ /** \brief Read the APSR register \details The function reads the Application Program Status Register (APSR) using the instruction \b MRS. \n\n The APSR contains the current state of the condition flags from instructions executed previously. The APSR is essential for controlling conditional branches. The following flags are used: - \b N (APSR[31]) (Negative flag) - =1 The instruction result has a negative value (when interpreted as signed integer). - =0 The instruction result has a positive value or equal zero. \n\n - \b Z (APSR[30]) (Zero flag) - =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same. \n\n - \b C (APSR[29]) (Carry or borrow flag) - =1 For unsigned additions, if an unsigned overflow occurred. - =<i>inverse of borrow output status</i> For unsigned subtract operations. \n\n - \b V (APSR[28]) (Overflow flag) - =1 A signed overflow occurred (for signed additions or subtractions). \n\n - \b Q (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0] - This flag is a \em sticky flag. Saturating and certain multiplying instructions can set the flag, but cannot clear it. - =1 When saturation or an overflow occurred. \n\n - \b GE (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0] - Can be set by the parallel add and subtract instructions. - Are used by the <kbd>SEL</kbd> instruction to perform byte-based selection from two registers. \returns APSR register value \remarks - Some instructions update all flags; some instructions update a subset of the flags. - If a flag is not updated, the original value is preserved. - Conditional instructions that are not executed have no effect on the flags. - The CMSIS does not provide a function to update this register. \sa - \ref __get_xPSR; APSR_Type - \ref ref_man_sec */ uint32_t __get_APSR(void); /**************************************************************************************************/ /** \brief Read the xPSR register \details The function reads the combined Program Status Register (xPSR) using the instruction \b MRS. \n\n xPSR provides information about program execution and the APSR flags. It consists of the following PSRs: \li Application Program Status Register (APSR) \li Interrupt Program Status Register (IPSR) \li Execution Program Status Register (EPSR) In addition to the flags described in \ref __get_APSR and \ref __get_IPSR, the register provides the following flags: - \b IT (xPSR[26:25]) (If-Then condition instruction) - Contains up to four instructions following an IT instruction. - Each instruction in the block is conditional. - The conditions for the instructions are either all the same, or some can be the inverse of others. \n\n - \b T (xPSR[24]) (Thumb bit) - =1 Indicates that that the processor is in Thumb state. - =0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup. - The conditions for the instructions are either all the same, or some can be the inverse of others. \returns xPSR register value \remarks - The CMSIS does not provide functions that access EPSR. \sa - \ref __get_APSR; __get_IPSR; xPSR_Type - \ref ref_man_sec */ uint32_t __get_xPSR(void); /**************************************************************************************************/ /** \brief Read the PSP register \details The function reads the Process Stack Pointer (PSP) value using the instruction \b MRS. \n\n Physically two different stack pointers (SP) exist: - The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode). - The Process Stack Pointer (PSP), which can be used only in thread mode. Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register: - =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory. - =1 PSP is the current stack pointer. The initial value is undefined. \returns PSP register value \remarks - Only one of the two SPs is visible at a time. - For many applications, the system can completely rely on the MSP. - The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code. \sa - \ref __set_PSP; __get_MSP; __get_CONTRO...
robert72001