/**************************** Data Structures ***********************************************/ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { #if (__CORTEX_M != 0x04) uint32_t _reserved0:27; ///< bit: 0..26 Reserved #else uint32_t _reserved0:16; ///< bit: 0..15 Reserved uint32_t GE:4; ///< bit: 16..19 Greater than or Equal flags uint32_t _reserved1:7; ///< bit: 20..26 Reserved #endif uint32_t Q:1; ///< bit: 27 Saturation condition flag uint32_t V:1; ///< bit: 28 Overflow condition code flag uint32_t C:1; ///< bit: 29 Carry condition code flag uint32_t Z:1; ///< bit: 30 Zero condition code flag uint32_t N:1; ///< bit: 31 Negative condition code flag } b; ///< Structure used for bit access uint32_t w; ///< Type used for word access } APSR_Type; /**************************************************************************************************/ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; ///< bit: 0.. 8 Exception number uint32_t _reserved0:23; ///< bit: 9..31 Reserved } b; ///< Structure used for bit access uint32_t w; ///< Type used for word access } IPSR_Type; /**************************************************************************************************/ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; ///< bit: 0.. 8 Exception number #if (__CORTEX_M != 0x04) uint32_t _reserved0:15; ///< bit: 9..23 Reserved #else uint32_t _reserved0:7; ///< bit: 9..15 Reserved uint32_t GE:4; ///< bit: 16..19 Greater than or Equal flags uint32_t _reserved1:4; ///< bit: 20..23 Reserved #endif uint32_t T:1; ///< bit: 24 Thumb bit (read 0) uint32_t IT:2; ///< bit: 25..26 saved IT state (read 0) uint32_t Q:1; ///< bit: 27 Saturation condition flag uint32_t V:1; ///< bit: 28 Overflow condition code flag uint32_t C:1; ///< bit: 29 Carry condition code flag uint32_t Z:1; ///< bit: 30 Zero condition code flag uint32_t N:1; ///< bit: 31 Negative condition code flag } b; ///< Structure used for bit access uint32_t w; ///< Type used for word access } xPSR_Type; /**************************************************************************************************/ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; ///< bit: 0 Execution privilege in Thread mode uint32_t SPSEL:1; ///< bit: 1 Stack to be used uint32_t FPCA:1; ///< bit: 2 FP extension active flag uint32_t _reserved0:29; ///< bit: 3..31 Reserved } b; ///< Structure used for bit access uint32_t w; ///< Type used for word access } CONTROL_Type; /**************************************************************************************************/ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8]; ///< Offset: 0x000 (R/W) Interrupt Set Enable Register uint32_t RESERVED0[24]; ///< Reserved __IOM uint32_t ICER[8]; ///< Offset: 0x080 (R/W) Interrupt Clear Enable Register uint32_t RSERVED1[24]; ///< Reserved __IOM uint32_t ISPR[8]; ///< Offset: 0x100 (R/W) Interrupt Set Pending Register uint32_t RESERVED2[24]; ///< Reserved __IOM uint32_t ICPR[8]; ///< Offset: 0x180 (R/W) Interrupt Clear Pending Register uint32_t RESERVED3[24]; ///< Reserved __IOM uint32_t IABR[8]; ///< Offset: 0x200 (R/W) Interrupt Active bit Register uint32_t RESERVED4[56]; ///< Reserved __IOM uint8_t IP[240]; ///< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) uint32_t RESERVED5[644]; ///< Reserved __OM uint32_t STIR; ///< Offset: 0xE00 ( /W) Software Trigger Interrupt Register } NVIC_Type; /**************************************************************************************************/ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; ///< Offset: 0x000 (R/ ) CPUID Base Register __IOM uint32_t ICSR; ///< Offset: 0x004 (R/W) Interrupt Control and State Register __IOM uint32_t VTOR; ///< Offset: 0x008 (R/W) Vector Table Offset Register __IOM uint32_t AIRCR; ///< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register __IOM uint32_t SCR; ///< Offset: 0x010 (R/W) System Control Register __IOM uint32_t CCR; ///< Offset: 0x014 (R/W) Configuration Control Register __IOM uint8_t SHP[12]; ///< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) __IOM uint32_t SHCSR; ///< Offset: 0x024 (R/W) System Handler Control and State Register __IOM uint32_t CFSR; ///< Offset: 0x028 (R/W) Configurable Fault Status Register __IOM uint32_t HFSR; ///< Offset: 0x02C (R/W) HardFault Status Register __IOM uint32_t DFSR; ///< Offset: 0x030 (R/W) Debug Fault Status Register __IOM uint32_t MMFAR; ///< Offset: 0x034 (R/W) MemManage Fault Address Register __IOM uint32_t BFAR; ///< Offset: 0x038 (R/W) BusFault Address Register __IOM uint32_t AFSR; ///< Offset: 0x03C (R/W) Auxiliary Fault Status Register __IM uint32_t PFR[2]; ///< Offset: 0x040 (R/ ) Processor Feature Register __IM uint32_t DFR; ///< Offset: 0x048 (R/ ) Debug Feature Register __IM uint32_t ADR; ///< Offset: 0x04C (R/ ) Auxiliary Feature Register __IM uint32_t MMFR[4]; ///< Offset: 0x050 (R/ ) Memory Model Feature Register __IM uint32_t ISAR[5]; ///< Offset: 0x060 (R/ ) Instruction Set Attributes Register uint32_t RESERVED0[5]; ///< Reserved __IOM uint32_t CPACR; ///< Offset: 0x088 (R/W) Coprocessor Access Control Register } SCB_Type; /**************************************************************************************************/ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1]; /*!< Reserved */ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register \note available for Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M33, Cortex-M33P, SecureCore SC300 */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register \note available for Cortex-M1, Cortex-M3 , Cortex-M4, Cortex-M7, Cortex-M33, Cortex-M33P, SecureCore SC000, SecureCore SC300 */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register \note available for Cortex-M33, Cortex-M33P */ } SCnSCB_Type; /**************************************************************************************************/ /** \brief Structure type to access the Implementation Control Block Register (ICB). \note replaces SCnSCB_Type (only on Cortex-M55/M85) */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } ICB_Type; /**************************************************************************************************/ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; ///< Offset: 0x000 (R/W) SysTick Control and Status Register __IOM uint32_t LOAD; ///< Offset: 0x004 (R/W) SysTick Reload Value Register __IOM uint32_t VAL; ///< Offset: 0x008 (R/W) SysTick Current Value Register __IM uint32_t CALIB; ///< Offset: 0x00C (R/ ) SysTick Calibration Register } SysTick_Type; /**************************************************************************************************/ /** \brief Structure type to access the In...
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