/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ // ==== IRQ Controller API ==== /** \defgroup irq_ctrl_gr Interrupts and Exceptions \brief Generic functions to access the Interrupt Controller. \details This section describes the device agnostic interrupt API viable for a wide range of specific interrupt controllers. The IRQ Controller API allows interrupt dependend applications to be easily portable across a wide range of controllers. \note The default implementation for \ref GIC_functions "Arm GIC (Generic Interrupt Controller)" can be found in \ref irq_ctrl_gic.c. It uses \c weak functions thus it can easily be overwritten by an alternative user implementation if needed. The Armv7-A architecture defines a common set of first level exceptions, see table below. | Exception | CMSIS Handler | Offset | Description | |-------------------------------|---------------|--------|-----------------------------------------------------------------------------| | Reset | Reset_Handler | 0x0000 | First instruction executed after reset. | | Undefined Instruction (Undef) | Undef_Handler | 0x0004 | Signals usage of an illegal instructions. | | Supervisor Call (SVC) | SVC_Handler | 0x0008 | Issued by software using SVC instruction. | | Prefetch Abort (PAbt) | PAbt_Handler | 0x000C | Signals a memory abort on istruction fetch. | | Data Abort (DAbt) | DAbt_Handler | 0x0010 | Signals a memory abort on data read or write. | | Hyp Trap | (NOP) | 0x0014 | Hypervisor instruction trap, only available with Virtualization Extensions. | | IRQ interrupt | IRQ_Handler | 0x0018 | Interrupt Request (typically from Interrupt Controller) | | FIQ interrupt | FIQ_Handler | 0x001C | Fast Interrupt Request (typically from Interrupt Controller) | By default those handlers are defined as weak empty functions by the \ref startup_c_sec "device specific startup code". Software and peripheral interrupts are all handled by one of the both central interrupt handlers (IRQ and FIQ). These needs to be implemented application specific. If an RTOS is used the interrupt handlers are typically provided by the RTOS, e.g. when using <a href="../../RTOS2/html/rtx5_impl.html">RTX5</a>. The interrupts available depends on the actual device in use. According to CMSIS specification the interrupts are defined as \ref IRQn_Type in \ref device_h_pg. Using the generic IRQ API one can easily enable and disable interrupts, set up priorities, modes and preemption rules, and register interrupt callbacks. \b Example: \code void SGI0_Handler() { /* * Handle Interrupt */ IRQ_ClearPending((IRQn_ID_t)SGI0_IRQn); } void main() { /* Initialize the Interrupt Controller */ IRQ_Initialize(); /* Register the user defined handler function */ IRQ_SetHandler((IRQn_ID_t)SGI0_IRQn, SGI0_Handler); /* Set the priority considering the priority grouping */ const uint32_t subprio = IRQ_GetPriorityGroupBits(); IRQ_SetPriority((IRQn_ID_t)SGI0_IRQn, 1u << subprio); /* Set interrupt mode to falling edge */ IRQ_SetMode((IRQn_ID_t)SGI0_IRQn, IRQ_MODE_TYPE_IRQ | IRQ_MODE_CPU_0 | IRQ_MODE_TRIG_EDGE | IRQ_MODE_TRIG_EDGE_FALLING); IRQ_Enable((IRQn_ID_t)SGI0_IRQn); /* Trigger interrupt */ IRQ_SetPending((IRQn_ID_t)SGI0_IRQn); IRQ_Disable((IRQn_ID_t)SGI0_IRQn); } \endcode @{ */ /** \defgroup irq_mode_defs IRQ Mode Bit-Masks \brief Configure interrupt line mode \details @{ The following codes are used as values for the parameter \em mode of the function \ref IRQ_SetMode to configure interrupt line mode. They are also returned by the function \ref IRQ_GetMode when retrieving interrupt line mode. The values of \b IRQ_MODE_TRIG_x definitions specify The values of \b IRQ_MODE_TYPE_x definitions specify The values of \b IRQ_MODE_DOMAIN_x definitions specify The values of \b IRQ_MODE_CPU_x definitions specify // Interrupt mode bit-masks \def IRQ_MODE_TRIG_LEVEL \def IRQ_MODE_TRIG_LEVEL_LOW \def IRQ_MODE_TRIG_LEVEL_HIGH \def IRQ_MODE_TRIG_EDGE \def IRQ_MODE_TRIG_EDGE_RISING \def IRQ_MODE_TRIG_EDGE_FALLING \def IRQ_MODE_TRIG_EDGE_BOTH \def IRQ_MODE_TYPE_IRQ \def IRQ_MODE_TYPE_FIQ \def IRQ_MODE_DOMAIN_NONSECURE \def IRQ_MODE_DOMAIN_SECURE \def IRQ_MODE_CPU_ALL \def IRQ_MODE_CPU_0 \def IRQ_MODE_CPU_1 \def IRQ_MODE_CPU_2 \def IRQ_MODE_CPU_3 \def IRQ_MODE_CPU_4 \def IRQ_MODE_CPU_5 \def IRQ_MODE_CPU_6 \def IRQ_MODE_CPU_7 \def IRQ_MODE_ERROR @} */ /** \defgroup irq_priority_defs IRQ Priority Bit-Masks \brief Definitions used by interrupt priority functions. \details @{ The following values are used by the interrupt priority functions. The value of \b IRQ_PRIORITY_Msk specifies maximum interrupt priority value and can be used as parameter for the functions \ref IRQ_GetPriority and \ref IRQ_SetPriorityGroupBits to retrieve implementation specific priority values. The value of \b IRQ_PRIORITY_ERROR is used by functions \ref IRQ_GetPriority, IRQ_GetPriorityMask and \ref IRQ_GetPriorityGroupBits to signal function execution error. \def IRQ_PRIORITY_Msk \def IRQ_PRIORITY_ERROR @} */ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \fn int32_t IRQ_Initialize (void) \details This function initializes interrupt controller. It disables all interrupt sources, clears all pending interrupts, sets interrupt priorities to highest priority and configures priority mask to lowest priority. IRQ and FIQ signal lines should be enabled and all interrupt handlers should be set to NULL. For Arm GIC the default implementation looks like the following example: \code /// Number of implemented interrupt lines #ifndef IRQ_GIC_LINE_COUNT #define IRQ_GIC_LINE_COUNT (1020U) #endif static IRQHandler IRQTable[IRQ_GIC_LINE_COUNT] = { 0U }; int32_t IRQ_Initialize (void) { uint32_t i; for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) { IRQTable[i] = (IRQHandler)NULL; } GIC_Enable(); return (0); } \endcode */ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \fn int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) \details This function registers address of the interrupt handler callback function corresponding to the specified interrupt ID number. For Arm GIC the default implementation looks like the following example: \code int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) { int32_t status; if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) { IRQTable[irqn] = handler; status = 0; } else { status = -1; } return (status); } \endcode */ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \fn IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) \details This function retrieves address of the interrupt handler callback function corresponding to the specified interrupt ID number. For Arm GIC the default implementation looks like the following example: \code IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) { IRQHandler h; if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) { h = IRQTable[irqn]; } else { h = (IRQHandler_t)0; } return (h); } \endcode */ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \fn int32_t IRQ_Enable (IRQn_ID_t irqn) \details This function enables forwarding of the corresponding interrupt to the CPU. For Arm GIC the default implementation looks like the following example: \code int32_t IRQ_Enable (IRQn_ID_t irqn) { int32_t status; if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) { GIC_EnableIRQ ((IRQn_Type)irqn); status = 0; } else { status = -1; } return (status); } \endcode */ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \fn int32_t IRQ_Disable (IRQn_ID_t irqn) \details This function disables forwarding of the corresponding interrupt to the CPU. For Arm GIC the default implementation looks like the following example: \code int32_t IRQ_Disable (IRQn_ID_t irqn) { int32_t status; if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) { GIC_DisableIRQ ((IRQn_Type)irqn); status = 0; } else { status = -1; } return (status); } \endcode */ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \fn uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) \details This function retrieves the interrupt enable status of the interrupt identified by the irqn parameter. Interrupt enable status can be either disabled (0) or enabled (1). Disabled status is returned for interrupts which cannot be identified by irqn. For Arm GIC the default implementation looks like the following example: \code uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) { uint32_t enable; if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) { enable = GIC_GetEnableIRQ((IRQn_Type)irqn); } else { enable = 0U; } return (enable); } \endcode */ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \fn int...
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