sketch.pdf

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LISA_REVERSE_A
5V TTL to 3.3V Interface
28
57
55
54
52
51
50
49
48
47
46
45
44
42
41
40
39
38
37
36
35
34
32
31
29
27
A
RGA8
RGA7
RGA6
RGA5
RGA4
RGA3
RGA2
RGA1
12
13
14
15
16
17
18
19
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
84
2
3
4
5
6
7
8
11
9
24
10
20
21
22
23
25
ZD
RGA8
RGA7
RGA6
RGA5
RGA4
RGA3
RGA2
RGA1
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
WIDE
!CAS
!RESET
CCK
MDAT
!MLD
SCLK
C14O
C28M
C28O
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
BLANK
1
13
3
4
7
8
11
14
17
18
21
22
12
U1
OE1
OE2
1A1
1A2
1A3
1A4
1A5
2A1
2A2
2A3
2A4
2A5
GND
VDD
1B1
1B2
1B3
1B4
1B5
2B1
2B2
2B3
2B4
2B5
VCC_5
24
C1
100n
2
5
6
9
10
15
16
19
20
23
R7
R6
R5
R4
R3
R2
R1
R0
HS
MIPI DPHY 1.8V
VCC
C2
100n
R2
1K5
R3
1K5
GND
MIPI3
MIPI1
MIPI0
MIPI2
R1
120
R4
47
R5
47
R6
120
GPIO
A
LP
LP
MP1
SN74CBTD3384PWLE
1
13
3
4
7
8
11
14
17
18
21
22
12
U2
OE1
OE2
1A1
1A2
1A3
1A4
1A5
2A1
2A2
2A3
2A4
2A5
GND
VDD
1B1
1B2
1B3
1B4
1B5
2B1
2B2
2B3
2B4
2B5
24
2
5
6
9
10
15
16
19
20
23
C3
100n
G7
G6
G5
G4
G3
G2
G1
G0
HS
R7
68
R8
68
CSI0_N
CSI0_P
GND
VCC
C4
100n
R13
1K5
R14
1K5
GND
CSICK_N
CSICK_P
HS
MIPI7
MIPI5
MIPI4
MIPI6
R11
120
R17
47
R21
47
R25
120
LP
GPIO
SCL
SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GND
R9
C5
MP2
J1
686115183522
LP
B
SN74CBTD3384PWLE
26
58
B
100n
GND
SOG
!BURST
1
13
3
4
7
8
11
14
17
18
21
22
12
U3
OE1
OE2
1A1
1A2
1A3
1A4
1A5
2A1
2A2
2A3
2A4
2A5
GND
VDD
1B1
1B2
1B3
1B4
1B5
2B1
2B2
2B3
2B4
2B5
HS
24
2
5
6
9
10
15
16
19
20
23
C6
100n
B7
B6
B5
B4
B3
B2
B1
B0
BLANK
CLK28
R27
68
R28
68
1K5
R10
1K5
R12
GND
1K5
DVI1
DVI2
43
VCC_5
LISA_REVERSE_B
1
33
53
30
56
83
GND
SN74CBTD3384PWLE
GND
G7
G6
G5
G4
G3
G2
G1
G0
R7
R6
R5
R4
R3
R2
R1
R0
SCL
SDA
B7
B6
B5
B4
B3
B2
B1
B0
HS
VS
C
C9
100n
GND
GND
BLANK
CLK28
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TANG9k
69
68
57
56
55
54
53
51
42
41
35
40
34
33
30
29
28
27
26
25
39
36
37
38
9k
3.3V
GND
32
31
49
48
5V
70
71
72
73
74
75
76
77
79
80
81
82
83
84
85
86
63
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VCC
C7
100n
GND
C8
100n
GND
VCC_5
DVI3
DVI4
DVI5
DVI6
DVI7
DVI8
MIPI7
MIPI6
MIPI5
MIPI4
MIPI3
MIPI2
MIPI1
MIPI0
D1
BAT54A
C
RGA Strobe Decoder
VCC
VCC
D2
BAT54A
R16
1K5
U5
A
B
C
OE1
OE2A
OE2B
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
GND
2
C12
GND
100n
16
15
14
13
12
11
10
9
7
$DFF38
C10
VCC
100n
GND
4
DVI RX Bias
5
$DFF38 || $DFF3A(VS)
D PRE Q
CLK
CLR Q
VS
VCC
RN1
C11
100n
DVI1
DVI2
DVI3
DVI4
200R
RN3
RN4
RN2
VCC
R15
1K5
VCC
3
RGA5
RGA8
RGA1
RGA2
RGA6
RGA7
1
2
3
6
4
5
8
U4A
SN74LVC74APW
6
7
GND
D3
BAT54A
1
14
VCC GND
VCC
100R
$DFF3A
D
RGA4
RGA3
$DFF3C
$DFF38
12
11
D PRE Q
CLK
CLR Q
9
$DFF3C (HS)
HS
200R
DVI5
DVI6
DVI7
DVI8
100R
10
D
SN74LVC138APWLE
GND
D4
BAT54A
1
2
3
8
U4B
SN74LVC74APW
GND
13
4
5
6
7
8
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