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M68331EVK/D
REV 1
October 1993
M68331EVK
EVALUATION KIT
USER’S MANUAL
© MOTOROLA, INC., 1991, 1993; All Rights Reserved
Motorola reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. Motorola does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part.
CPU32Bug is a trademark of Motorola Inc.
White Knight is a trademark of FreeSoft Company.
MacTerminal, Apple, and Macintosh are trademarks of Apple Computer, Inc.
IBM-PC is a registered trademark of International Business Machines Corporation.
ProComm is a trademark of Datastorm Technologies,Inc.
The computer program stored in the Read Only Memory of the device contains material
copyrighted by Motorola Inc., first published 1991, and may be used only under a license such as
the License For Computer Programs (Article 14) contained in Motorola’s Terms and Conditions
of Sale, Rev. 1/79.
TABLE OF CONTENTS
TABLE OF CONTENTS
CHAPTER 1 GENERAL INFORMATION
1.1
1.2
1.3
1.4
1.5
Introduction......................................................................................................................... 1-1
Features............................................................................................................................... 1-1
Specifications...................................................................................................................... 1-2
General Description ............................................................................................................ 1-4
Equipment Required ........................................................................................................... 1-5
CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION
2.1 Introduction......................................................................................................................... 2-1
2.2 Unpacking Instructions....................................................................................................... 2-1
2.3 Hardware Preparation ......................................................................................................... 2-1
2.3.1 BCC Configuration .................................................................................................. 2-3
2.3.1.1 RAM Chip Enable Select Header (J2)............................................................. 2-4
2.3.1.2 EPROM Chip Select Header (J3).................................................................... 2-5
2.3.1.3 TxD Select Header (J4) ................................................................................... 2-6
2.3.1.4 RxD Select Header (J5)................................................................................... 2-7
2.3.1.5 Clock Input Select Header (J6)........................................................................ 2-8
2.3.2 PFB Configuration ................................................................................................. 2-10
2.3.2.1 U1 and U3 Enable Header (J1)...................................................................... 2-12
2.3.2.2 U2 Enable Header (J2) .................................................................................. 2-13
2.3.2.3 U4 Enable Header (J3) .................................................................................. 2-14
2.3.2.4 U2 RAM/EPROM Select Header (J4)........................................................... 2-15
2.3.2.5 U2 EPROM Select Header (J5)..................................................................... 2-16
2.3.2.6 U4 EPROM Select Header (J6)..................................................................... 2-17
2.3.2.7 U4 RAM/EPROM Select Header (J7)........................................................... 2-18
2.3.2.8 Revision Level Select Headers (J8 - J13)...................................................... 2-19
2.3.2.9 IFETCH Select Header (J14)........................................................................ 2-20
2.3.2.10 Coprocessor Socket (U5)............................................................................... 2-22
2.4 Installation Instructions .................................................................................................... 2-23
2.4.1 BCC – PFB Interconnection................................................................................... 2-23
2.4.2 Target System – BCC Interconnection................................................................... 2-24
2.4.3 Power Supply – EVK Connection.......................................................................... 2-27
2.4.4 Terminal – EVK Connection.................................................................................. 2-28
2.4.5 Terminal – BCC Connection.................................................................................. 2-30
2.4.6 Logic Analyzer – EVK Connection ....................................................................... 2-32
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MOTOROLA
TABLE OF CONTENTS
CHAPTER 3 OPERATING INSTRUCTIONS
Introduction......................................................................................................................... 3-1
General Information............................................................................................................ 3-2
Control Switches................................................................................................................. 3-3
Limitations.......................................................................................................................... 3-3
3.4.1 Chip Select Usage .................................................................................................... 3-4
3.4.2 Other MCU Resources Used by CPU32Bug............................................................ 3-5
3.5 Operating Procedure ........................................................................................................... 3-7
3.6 Monitor Description............................................................................................................ 3-8
3.6.1 Memory And Register Display And Modification Commands................................ 3-9
3.6.2 Breakpoint Capabilities ............................................................................................ 3-9
3.6.3 System Calls ........................................................................................................... 3-10
3.6.4 Diagnostic Monitor................................................................................................. 3-12
3.7 Assembling/Disassembling Procedures............................................................................ 3-14
3.8 Downloading Procedures.................................................................................................. 3-18
3.8.1 Apple Macintosh (with MacTerminal) to EVK...................................................... 3-19
3.8.2 Apple Macintosh (with White Knight) to EVK ..................................................... 3-21
3.8.3 IBM-PC (with KERMIT) to EVK.......................................................................... 3-22
3.8.4 IBM-PC (with PROCOMM) to EVK..................................................................... 3-23
CHAPTER 4 FUNCTIONAL DESCRIPTION
4.1
4.2
4.3
Introduction......................................................................................................................... 4-1
EVK Description ................................................................................................................ 4-1
BCC Description................................................................................................................. 4-3
4.3.1 MCU Summary ........................................................................................................ 4-4
4.3.1.1 32-Bit Central Processor Unit ......................................................................... 4-4
4.3.1.2 General-Purpose Timer ................................................................................... 4-5
4.3.1.3 Queued Serial Module..................................................................................... 4-5
4.3.1.4 External Bus Interface ..................................................................................... 4-6
4.3.1.5 Chip Selects..................................................................................................... 4-6
4.3.1.6 System Clock................................................................................................... 4-6
4.3.1.7 Test Module..................................................................................................... 4-6
4.3.2 User Memory............................................................................................................ 4-6
4.3.3 I/O Connectors ......................................................................................................... 4-8
4.3.3.1 64-Pin Expansion Connectors ......................................................................... 4-8
4.3.3.2 Serial Communication Connectors.................................................................. 4-8
4.3.3.3 Background Mode Interface Connector .......................................................... 4-8
4.4 PFB Description ................................................................................................................. 4-8
4.4.1 Floating-Point Coprocessor Socket (U5) ................................................................. 4-8
4.4.2 Logic Analyzer Connectors...................................................................................... 4-9
3.1
3.2
3.3
3.4
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MOTOROLA
TABLE OF CONTENTS
CHAPTER 5 SUPPORT INFORMATION
5.1
5.2
Introduction......................................................................................................................... 5-1
Connector Signal Descriptions ........................................................................................... 5-1
APPENDIX A S-RECORD INFORMATION
LIST OF ILLUSTRATIONS
Figure
2-1
2-2
2-3
2-4
2-5
2-6
2-7
4-1
4-2
4-3
Page
M68331EVK Evaluation Kit .............................................................................................. 2-2
BCC Jumper Header and Connector Location Diagram .................................................... 2-3
PFB Jumper Header and Connector Location Diagram ................................................... 2-11
Expansion Connector Pin Assignments............................................................................ 2-25
Target System Connector Dimension Requirements........................................................ 2-26
Terminal/PC Cable Diagram for PFB P9 ......................................................................... 2-29
Terminal/PC Cable Diagram for BCC P4 ........................................................................ 2-31
EVK Block Diagram........................................................................................................... 4-2
BCC Block Diagram........................................................................................................... 4-3
EVK Memory Map ............................................................................................................. 4-7
M68331EVK/D
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MOTOROLA

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