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APR16/D
Calculating Time
Requirements of
External SRAM
for the
24-bit DSP56000 Family
Digital Signal
Processors
M o t o r o l a ’ s
H i g h - P e r f o r m a n c e
D S P
T e c h n o l o g y
Table of Contents
SECTION 1
SECTION 2
Introduction
SRAM Interface
2.1
2.2
2.3
2.4
System Description
Read Timing
Write Timing
Calculating T
C
and T
L
2.4.1 Example 1
2.4.2 Example 2
2-1
2-2
2-4
2-5
2-6
2-8
1-1
SECTION 3
Additional Considerations
3.1
3.2
3.3
3.4
3.5
3.6
Glue Logic
Maximum and Minimum Specifications
Additional Specifications to Meet
Different Timing Specifications
Wait States
Asynchronous vs. Synchronous Timing
3-1
3-1
3-2
3-3
3-3
3-4
4-1
References-1
SECTION 4
Summary
REFERENCES
MOTOROLA
iii
Illustrations
Figure 2-1
Figure 2-2
Figure 2-3
DSP56002 Interface to External SRAM
Read Cycle Timing Diagram
Write Cycle Timing Diagram
2-2
2-3
2-4
MOTOROLA
v
List of Tables
Table 2-1
Formulas for T
H
, T
L
, and T
C
2-6
MOTOROLA
vii
SECTION 1
Introduction
I
nterfacing the DSP56000 family digital signal processors (DSPs) to external
SRAM involves timing parameters that are dependant on the DSP’s configuration.
The external clock and the configuration of the phase-locked loop (PLL) affect the
internal clock’s behavior which in turn determines the necessary speed of external
SRAM. Timing parameters are also affected by the configuration of signals that the
DSP uses to access the SRAM.
This application note is a tutorial on calculating timing requirements for interfac-
ing members of the DSP56000 family to external SRAM. While the examples and
discussion center around the DSP56002, the approaches presented may also be ap-
plied to other members of the DSP56000 family that have an external bus.
Note:
Specifications herein are based on preliminary data sheets. Any designs of a sys-
tem using a member of the DSP56000 family should be based on the latest
revision of the appropriate Technical Data Sheet. (See the REFERENCES section
s
for a listing of relevant manuals and data sheets.)
MOTOROLA
1-1
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