APR3.pdf

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APR3/D
Rev. 1
Fractional and
Integer Arithmetic
using the
DSP56000 Family of
General-Purpose
Digital Signal
Processors
M o t o r o l a ’ s
H i g h - P e r f o r m a n c e
D S P
T e c h n o l o g y
Table
of Contents
SECTION 1
Introduction
1-1
SECTION 2
Data
Representations
2.1 Twos-Complement Fraction
2.1.1 Twos-Complement Integer
2.2 Double-Precision Numbers
2.3 Real Numbers
2.4 Mixed Numbers
2.5 Data Shifting
2.5.1 1-Bit Shifts/Rotates
2.5.2 Multi-Bit Shifts/Rotates
2.5.3 Fast Multi-Bit Shifts
2.5.4 No-Overhead, Dynamic Scaling
(1-Bit Shifts)
3.1 Mixed Numbers
3.1.1 Addition
3.1.2 Subtraction
3.2 Real Numbers
3.2.1 Addition
3.2.2 Subtraction
2-1
2-4
2-6
2-6
2-10
2-14
2-14
2-15
2-16
2-20
3-1
3-1
3-3
3-4
3-4
3-6
SECTION 3
Mixed- and
Real-Number
Addition and
Subtraction
MOTOROLA
iii
Table
of Contents
SECTION 4
Signed
Multiplication
4.1 Multiplication of a Signed Fraction with a
Signed Fraction
4.2 Multiplication of a Signed Integer with a
Signed Integer
4.3 Multiplication of a Signed Integer with a
Signed Fraction
4.4 Double-Precision Multiplication
4.5 Double-Precision Multiplication
of Fractions
4.6 Double-Precision Multiplication of
Integers
4.7 Multiplication of a Real Number with a
Real Number
4.8 Multiplication of a Mixed Number with
a Mixed Number
5.1 Division of a Signed Fraction by a
Signed Fraction
5.2 Division of a Signed Integer with a
Signed Integer
5.3 Double-Precision Division
5.4 Real-Number Division
5.5 Mixed-Number Division
5.6 Divide Routines with N
≤
24 Bits
5.6.1 Positive Operands with
Remainder Where N Is Variable
5.6.2 Positive Operands without
Remainder Where N Is Fixed
4-3
4-4
4-5
4-7
4-7
4-10
4-12
4-16
SECTION 5
Signed Division
5-3
5-8
5-10
5-14
5-16
5-18
5-18
5-18
iv
MOTOROLA
Table
of Contents
5.6.3 Signed Operands with Remainder
Where N Is Variable
5-20
5.6.4 Signed Operands without
Remainder Where N Is Fixed
5-21
SECTION 6
Conclusion
6-1
REFERENCES
References-1
MOTOROLA
v
Illustrations
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-7
Figure 2-8
Figure 2-9
Figure 2-10
Figure 2-11
Figure 2-12
Twos-Complement Fraction
DSP56000 Operands
Twos-Complement Integers
Real-Number Format
CONVR Macro Definition
CONVRG Macro Definition
Mixed Number Format
CONVMN Macro
CONVMNG Macro Definition
Multi-Bit Shifts Using REPeat, DO
Multi-Bit Shift Macros
Constant Generation and Multi-Bit Shifts
2-2
2-3
2-5
2-7
2-8
2-8
2-11
2-11
2-13
2-15
2-16
2-19
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Signed-Integer Multiplication
Signed-Fraction Multiplication
CONVSISF Routine
Double-Precision Multiplication
MULT48FG Flowchart
MULT48FG Routine
MULT48IG Routine
4-1
4-2
4-6
4-7
4-9
4-10
4-13
MOTOROLA
vii

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