DSP56303CE0F94R.pdf

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Chip Errata
DSP56303 Digital Signal Processor
Mask: 0F94R
General remark: In order to prevent the usage of instructions or sequences of instructions
that do not operate correctly, the user is encouraged to use the “lint563” program to identify
such cases and use alternative sequences of instructions. This program is available as part of
the Motorola DSP Tools CLAS package.
Silicon Errata
Errata
Number
Errata Description
Description (added 2/18/1996):
ES2
The DSP56303 cannot work with a low frequency crystal (less than 500
KHz) connected as its clock source between EXTAL and XTAL pins.
Workaround:
Not available
Description (added 2/18/1996):
If any DMA channel is active and a second DMA channel is enabled by
writing
DE = 1 and TM = 011 to its control register, and the next instructions
cause “transfer stall” (see Appendix B-3.4.2 in the DSP56300 core
specification) or “conditional transfer interlock” (see paragraph B-3.5.1
in the DSP56300 core specification), then the second DMA channel does
not start data transfer.
Workaround:
Insert one NOP instruction between the DMA control register write and
the sequence causing the “transfer stall” or “conditional transfer
interlock”. Do not place a write instruction to the DMA control register
with DE = 1 and
TM = 011 as a second word of a fast interrupt routine.
0F94R
Applies
to Mask
0F94R
ES3
Motorola SPS
303CE0F94R_4.0
6501 William Cannon Drive West, Austin, Texas 78735-8598
pg. 1 /ng/7/17/00
©
1996–1999 Motorola
Chip Errata
DSP56303 Digital Signal Processor
Mask:0F94R
Errata
Number
Errata Description
Description (added 2/18/1996):
Applies
to Mask
0F94R
ES4
Two sequential 1-cycle writes to the same peripheral do not work
properly.
Workaround:
Not available
Description (added 2/18/1996):
When external bus activity is disabled (OMR[4] is set) and there is a
contention between the DMA and core access to internal memory
(access to the same 256-word bank), the DMA does not function
properly.
Workaround:
Do not disable external bus activity (do not set OMR[4]) if the DMA will
be used.
Description (added 2/18/1996):
When the stack extension is enabled and a nested DO loop with
consecutive LAs ends causing SP to return to 0, a stack extension
operation which fills the HW stack is wrongly executed (but no stack
error occurs), causing EP to be decremented under its lowest permitted
value. If this section of the memory belongs to another program task,
damage will be caused because of stack extension operation that will
overwrite these two memory locations (EP-1 and EP-2).
Workaround:
Any of the following alternatives can be used:
a.
Guarantee that EP-1 and EP-2 memory locations are not used by
any task.
b.
c.
Separate the two consecutive LAs by one instruction.
Push a dummy value onto the stack before the nested DO loop.
0F94R
0F94R
ES5
ES6
DSP56303 Errata
©
1996–1999 Motorola
303CE0F94R_4.0
pg. 2 /ng/7/17/00
Chip Errata
DSP56303 Digital Signal Processor
Mask:0F94R
Errata
Number
Errata Description
Description (added 2/18/1996):
Applies
to Mask
0F94R
ES7
The STOP instruction does not work properly.
Workaround:
Not available
Description (added 2/18/1996):
The IRQA, IRQB, IRQC, IRQD, PINIT/NMI, HCLK, and RESET pins do
not have the proper 5 volt protection.
0F94R
ES8
Workaround:
Not required. The pins function correctly as specified. There is no
significant reliability degradation expected. It is recommended that the
system apply only 3.3 volt levels to these pins if possible.
Description (added 2/18/1996):
Stack extension mechanism does not work properly if a conditional
jump or branch to subroutine is used.
Workaround:
For the proper operation, the following instructions should not appear
immediately after conditional jump or branch to subroutine:
XY Memory Data Move (A-6.76)
X Memory Move (A-6.71)
Y Memory Move (A-6.73)
Long Memory Data Move (A-6.75)
Immediate Short Data Move (A-6.68)
Register to Register Data Move (A-6.69)
Address Register Update (A-6.70)
X Memory and Register Data Move (A-6.72)
Y Memory and Register Data Move (A-6.74)
Arithmetic Instructions that allow Parallel Moves listed above
IFcc and IFcc.U (A-6.41)
Note: For this workaround, any of the listed above instructions should
not be the first instruction of interrupt service routine.
0F94R
ES10
DSP56303 Errata
©
1996–1999 Motorola
303CE0F94R_4.0
pg. 3 /ng/7/17/00
Chip Errata
DSP56303 Digital Signal Processor
Mask:0F94R
Errata
Number
Errata Description
Description (added 2/18/1996):
When the DMA channel is enabled in triggered by request mode and the
core is in the WAIT state, a false DMA data transfer might occur (e.g.,
one DMA request might cause two data transfers instead of one).
Workaround:
Not available
Description (added 2/18/1996):
When the DMA performs external memory accesses with priority
higher than the core and both continuous mode and interrupt enable
bits are set in the channel’s control register, then the DMA interrupt
might not occur if the core performs external memory access
immediately after the enabling (DE = 1) of the DMA channel.
Applies
to Mask
0F94R
ES11
0F94R
ES14
Workaround:
In this scenario any of the following alternatives can be used:
a.
b.
Do not set continuous mode.
Use dynamic DMA-core priority.
c.
Guarantee that the core will perform at least two instructions
fetched from
internal memory immediately after setting of the DE.
Description(added 2/18/1996):
While stack extension is enabled and MOVE to/from SSH is followed by
Address Generation Interlock of Type0, then improper operation may
occur. For example, the following sequence may generate incorrect
results:
ES15
MOVE SSH,A
MOVE #0,R7
MOVE A,X:(R7)
0F94R
Workaround:
After MOVE to/from SSH use any instruction sequence that does not
cause Address Generation Interlock of Type0.
Note: No interrupt service routine should start with Address
Generation Interlock of Type0).
DSP56303 Errata
©
1996–1999 Motorola
303CE0F94R_4.0
pg. 4 /ng/7/17/00
Chip Errata
DSP56303 Digital Signal Processor
Mask:0F94R
Errata
Number
Errata Description
Description (added 2/18/1996):
When the chip is powered up with PLL enabled (PINIT = 1), the skew
between
EXTAL and CLKOUT after the PLL locks cannot be guaranteed at high
frequency (over 50 MHz, not 100% tested).
Workaround:
If skew between EXTAL and CLKOUT is needed, power up with PINIT
= 0, and then enable the PLL by software.
Applies
to Mask
0F94R
ES16
DSP56303 Errata
©
1996–1999 Motorola
303CE0F94R_4.0
pg. 5 /ng/7/17/00

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