FAQ1.pdf

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Deleting Memory Bus Tranceivers
Q:
Why are buffers required between the MPC106 and memory? Can they be elimi-
nated?
The buffers are required to both minimize loading on the processor data bus and provide
additional data setup/hold time for high-speed memory designs. Refer to application
note AN1xxx, “SDRAM System Design using the MPC106” for greater detail, from
whence the following table is extracted:
Recommended Buffer
Capacitive Load
Bus Speed
≥
83 MHz
Type
Registered
Example
16501
16601
162601
16245
162245
-
A:
High or Low
High
Low
≤
66 MHz
≤
66 MHz
Flow-through
None
This table shows that the buffers may be deleted when the capacitive loading is kept
small (
≤
50 pF) and the bus frequency is not too fast (
≤
66 MHz).
NOTE
: These are general guidelines. A full simulation of the target design may reveal
that buffers are needed even at slow frequencies, or may reveal that faster operation is
possible. The answer is heavily dependant upon the type and number of components
chosen, and the PCB layout.

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