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Jitter vs. Skew

Why is jitter speciﬁed so tightly? How can I keep all the devices on the PowerPC bus

accurate to within the

150 ps limits?

PowerPC processors (and the MPC106) use a PLL-based (Phase-Locked Loop) clock

generator, which synthesizes high frequencies but maintains alignment between the mul-

tiplied clock and the input clock (SYSCLK). PLL’s normally ﬁlter out small amounts of

jitter that affect the alignment of each clock edge (this is called “short-term jitter”), and

maintain a steady, constant edge on the outputs in the face of this error. If this limitation

is exceeded, the PLL may attempt to “re-lock” to what appears to be a completely new

frequency. While the PLL is attempting to re-capture the clock edge, the output accu-

racy may fail, possibly causing a system failure.

However, this jitter restriction should not be confused with skew; while jitter is a func-

tion of the clock input section of the PLL, skew is a function of clock-to-output AC tim-

ing, output loading, etc. while the former is a function of the PLL clock input. As

explained elsewhere in this FAQ, the PowerPC family is much more tolerant of clock-to-

clock skew.

Thus, while designing a PowerPC system, it is not the case that clocks must be “accu-

rate” to within

150ps, only that the cycle-to-cycle jitter of each separate clock be within

150ps. The clocks could all be skewed 500ps relative to each other, and the system

should still work reliably.