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Athur Load Pipelining

Q: When using the Arthur 740 CPU, we have noticed the following apparent

poor behavior on the system bus:

Arthur seems to be unable to pipeline a burst read access on the bus. That is,

it waits for the TA_ assertion (and not AACK_ assertion) of the previous read

cycle to issue the next TS_ of a read. Arthur requests the bus after the last

TA_ for reads; the same situation occurs when the address bus is parked to

Arthur. The net effect for our systems is very bad: the DRAM available read

bandwidth dropped from a 200 MB/s usable bandwidth (measured with a 604 and

604e) down to 100 MB/s. Is that behaviour normal for Arthur?

All 603 parts, including Arthur, have never pipelined more than one load

at a time. The L1 cache is blocking by design. That is, once it gets a cache

miss, it cannot handle another cache miss until the 1st one has completed

in its entirety. Also, this is independent of address. This was part of the

simpliﬁed design stratagy of the 603 family as compared to the 604 family.

It's not until G4 that these two families converge in this respect.

Note that some general pipelining is possible on the bus as follows. Since

I and D caches are seperate, each one can have one miss outstanding, so

you could pipeline an instruction fetch with a d-side load (or with a

cacheable store miss - which looks like a load to the biu). Also, all

writes on the bus (single-beat or burst) are queued in the biu, so they

can be pipelined among themselves and among i-fetches and d-reads.