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PowerPC Maximum Clock Jitter

Q: What happens if a system design fails to meet the PowerPC speciﬁcation

for maximum clock jitter?

Jitter in the input clock adds uncertainty to the microprocessor's input

and output timing, see the question above.

One customer reported an input clock thar varied (jittered) from it's ideal

position by plus or minus 2ns cycle to cycle; hence the clock period varied from

33ns to 37ns. The system design must have sufﬁcient margin to tolerate that varia-

tion. One laboratory test of margin is to operate the board at the increased fre-

quency (1/33ns or 30.4MHz) and see if it still works reliably at all operating

conditions.

The PowerPC microprocessor will have a frequency dependent response to the

input jitter. For relatively low frequency deviation from the ideal clock, these PLLs

will track the jitter very closely. At higher frequency jitter the response of the PLLs

may vary. They may not track as well as the frequency gets higher and they may

develop phase error with regard to the input clock. This will not affect their

operation but may change the AC timing of signals that will then be internally gen-

erated by this out-of-phase internal clock. Output valid time might appear longer,

for example, when measured to the input clock, because the internal clock is

slightly delayed from the input because it can't track the jitter fast enough.

In a worst case condition, if the input jitter modulation approaches the

resonant frequency of our PLL (200kHz to 1MHz across process variations) the

processor could amplify the jitter and have more jitter on it's output than

came in on the input. That wouldn't be disastrous necessarily; it would only

again degrade our AC timing accuracy.

This analysis parallels the discussion of input clock rise and fall time

above. The system design would have to change the AC timings to account

for the uncertainty introduced by the increased jitter.