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Performance of PCI to system DRAM

I am attempting to give a customer a worst-case number for throughput from

their PCI master to system DRAM using the 106. On page 7-3 of the 106 UM,

we are told that the 106 can accept burst writes of up to 32 bytes without wait

states.

Does this mean that the 106 will target-abort after 32 bytes or simply insert

wait states, and if so, how many (worst case)?

The 106 will not target-abort after 32-bytes, it will target-disconnect. The

distinction being a 'target-abort' tells the master that the target will never

be able to ﬁnish the transaction; the 'target-disconnect' tells the master

that the target is unable to process any more data at the moment, but the

master should resume the transaction at a later time. The 32-byte limit is

because the internal PCI-to-system-memory-write-buffer (PCMWB), which is

32-bytes, must snoop the address on the 60x bus and ﬂush its contents to

system memory. There is a pretty thorough coverage of this in Section 8.1.3.2

and Section 7.4.3.2 in the 106 User's Manual.

There is also a performance paper that the 106 design team presented at the PCI

Design conference in 95 or 96 with a good primer on calculating PCI

throughput. The document is titled, The Performance and PowerPC Platform

Implementation of the MPC106 Chipset, by Bryant, Garcia, Reynolds, Weber,

and Wilson. This paper is available on our Technical Support website.