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Attaching 8/16-bit Peripherals to the PowerPC Data Bus
Q:
A:
Can 8 or 16-bit peripherals be attached to the PowerPC bus directly?
Yes, there are many ways to do this. If the system uses the MPC106, one easy technique is to
use the ROM data bus. The MPC106 provides two ROM chip selects, RCS0* and RCS1*. In
may cases, the first ROM is the boot ROM, and the second is unused. As this decoder is for a 64-
bit ROM only, up to eight 8-bit devices or four 16-bit devices (or some mixture thereof) may be
attached using the same RCS1* signal, as shown in the following diagram.
MDH(0:7)
MDH(8:15)
MDH(16:23)
BUFFERED POWERPC DATA BUS
MDH(24:31) MDL(0:7)
MDL(8:15)
MDL(16:23)
MDL(24:31)
D(7:0)
AR(17:20)
DCS1
FOE
WE
A(3:0)
CS
OE
R/W
F139
DCS1
AR(10:12)
DCS2
RCS1
CS
AR(17:20)
DCS2
FOE
WE
D(15:0)
A(3:0)
CS
OE
R/W
The ROM control signals are equivalent to those typically found on I/O peripherals. The data
bus bits should be transposed if the device is “little-endian”, as most are, when connected to the
“big-endian” PowerPC data bus. Similarly, the ROM address bits are also transposed. Do NOT
use the processor address bus; instead use the ROM address bus specifically generated by the
MPC106. The F139 decoder divides the chip selects among multiple peripherals; if only one
device is present it may be removed.
It is also possible to use the first ROM space (RCS0*) by providing additional address decoding,
assuming that the entire 8 Mbyte space is not used by the boot ROM. External decoders can
sub-divide the ROM address space to select the ROM and the other devices as well.
The disadvantage of using the ROM space for I/O is that there is only one timing constant, con-
trolled by the ROMFAL and ROMNAL fields of the MPC106. Thus, all I/O devices must oper-
ate at the speed of the slowest device; perhaps 150 ns per access.
Alternately, if an MPC106 is not used, then interfacing may be a little more difficult. Decoding
the PowerPC bus requires monitoring A(0:xx), TT(0:3), TSIZ(0:2), BG*, DBG*, ABB*, DBB*,
ARTRY* and possibly DRTRY*. The logic must then asset the I/O device controls, plus gener-
ate AACK* and TA* at the appropriate time. This can be implemented in a programmable gate
array.

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