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Power Supply Sequencing

I derive the core voltage (VDD) for a PowerPC CPU from an second-level switching

power supply powered from my main power supply. Since it powers up last , how can I

meet the restriction that I/O voltage (OVDD) must not exceed the core voltage (VDD) by

1.2V at any time?

This situation is shown in the following diagram:

3.3V (OVDD)

2.5V (VDD)

Voltage

t, ms

Hazard

Although the speciﬁcations do require the restrictions on voltage differentials, it should

be noted that these are static differences. If the “ramp” time is kept below 500µsec, the

part will not suffer any damage. Keeping the part in reset will minimize the amount of

current needed and will provide a small amount of additional margin.

If it is not possible to achieve this, a so-called “bootstrap” diode may be installed

between OVDD and VDD as shown below.

Main Power

3.3V (OVDD)

MUR420 x 2

Core Power

2.5V (VDD)

The device is selected so that a nominal VDD is provided from the OVDD power supply until the

VDD power supply becomes active. In the above example, a schottky diode that provides a 1.2V

will keep the VDD line at 2.1V until the VDD power supply ramps up to 2.5V. At that time,

the diode will be reverse biased and very little current will ﬂow. In the example above, two

MUR420 devices are used to provide 0.6V each.