MPC2605FACT.pdf

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Fa c t S h e e t
MPC2605FACT/D
Rev. 3
Motor ola MPC2605
Integrated Secondar y Cache for PowerPC
™
Micr opr ocessor Applications
A member of the PowerPC family of components, the MPC2605 groups together all the functions required to
implement a level 2 cache design integrated into one chip, eliminating the need for glue logic.
Product Description
The MPC2605 is a single chip 256 KByte integrated look-aside cache with copy-back capability. It integrates
data, tag, host interface, and least recently used (LRU) memory with a cache controller. The 32K x 72 bit mem-
ory array is organized in a four-way set associative cache design. The 8K x 18 bit integrated tag is associated
similarly. The four ways are prioritized in a separate 2K x 8 bit LRU buffer. The cache controller handles bus
transactions per the 60X bus interface protocol. One, two, or four of these integrated cache devices can be cas-
caded to provide 256 KB, 512 KB, or 1 MB of level 2 cache, respectively. Implementation of the different
cache sizes as well as the arbitration between the caches in a multi-cache design is performed internally with the
use of configuration pins. The control logic is designed to support up to four processors in a shared cache sys-
tem. A write-through control pin is included to operate the cache in a write-through or copy-back cache
design. Additional non-60X bus signals are also incorporated into MPC2605 for flexible interface with other
arbiters.
Product Highlights
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Single 3.3 V Power Supply
83 MHz Zero Wait State Performance
Single Chip L2 Cache for 60X bus Applications
32 K x 64 Data Memory Array with Parity
8 K x 18 Tag Array
Four Way Set Associative Cache Design
LRU Cache Control Logic
Copy Back or Write Through Modes of Operation
Address Parity Support
Supports up to Four Processors as a Shared Cache
Depth Expandable to 64 K x 64 or 128 K x 64 with
Parity
Applications
The MPC2605 is specifically designed for 60X bus applications. It is ideal for MPC603e, MPC604, MPC740,
MPC860, and MPC8260 applications needing level 2 cache for an improvement in system level performance.
continued on back
MPC2605 Block Diagram
TRST
TMS
TDI
60X Bus
Interface
CFG
L2 Claim
L2 Flush
L2MissInh
L2TagClr
L2UpdateInh
APEN
A,AP
Controller
and Bus
Interface
JTAG
TCK
TDO
Copy-Back
Buffer
8K x 72 x4
Data Array
DH
DL
DP
2K x 8 LRU
2K x 18 x 4
Tag RAM
Compare
Contact Information
Motorola offers data sheets, application notes and models for Fast Static RAM products. In addition,
more information is provided for these products at:
http://mot-sps.com/products
For all other inquiries about Motorola products, please contact the Motorola Customer
Response Center: phone: 800-521-6274 or
http://www.motorola.com/semiconductors
© 2000 Motorola, Inc. All rights reserved. Printed in the U.S.A. Motorola, the
, and Digital DNA and the Digital DNA logo are registered trademarks of Motorola, Inc. This document con-
tains information on a new product under development. Specifications and information herein are subject to change without notice.

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