/*********************************************************************** Purpose: Typical RESET sequence including memory programming on the MPC106, setting up BAT registers, and others. Pretty detailed code sequence. ***********************************************************************/ // // Define processor identification. // #define MPC601 1 #define MPC603 3 #define MPC604 4 #define MPC602 5 #define MPC603E 6 #define MPC603M 0x58 #define MPC603EV 7 #define MPC750 8 #define MPC604PLUS 9 #define READ_EAGLE_REGISTER_UCHAR(EAGLE_REGISTER) \ LWI (r.23, EAGLE_ADDR_REG) ;\ LWI (r.24, 0x80000000 + EAGLE_REGISTER) ;\ rlwinm r.3, r.24, 0, 3 ;\ rlwinm r.24, r.24, 0, ~3 ;\ stwbrx r.24, 0, r.23 ;\ sync ;\ LWI (r.23, EAGLE_DATA_REG) ;\ lbzx r.3, r.3, r.23 ;\ sync #define SIMM_SPEED r.25 #define EAGLE_VERSION r.27 #define MEMORY_BUS_SPEED r.28 #define MEMORY_SIZE_ERROR r.29 #define PROCESSOR_TYPE r.30 #define MEMORY_SIZE r.31 #define READ_EAGLE_REGISTER_ULONG(EAGLE_REGISTER) \ LWI (r.23, EAGLE_ADDR_REG) ;\ LWI (r.24, 0x80000000 + EAGLE_REGISTER) ;\ stwbrx r.24, 0, r.23 ;\ sync ;\ LWI (r.23, EAGLE_DATA_REG) ;\ lwbrx r.3, 0, r.23 ;\ sync #define BANK7_ENABLE 0x80 #define BANK6_ENABLE 0x40 #define BANK5_ENABLE 0x20 #define BANK4_ENABLE 0x10 #define BANK3_ENABLE 0x8 #define BANK2_ENABLE 0x4 #define BANK1_ENABLE 0x2 #define BANK0_ENABLE 0x1 #define MEMORY_STARTING_ADDR_0_REGISTER 0x80 #define MEMORY_STARTING_ADDR_4_REGISTER 0x84 #define MEMORY_ENDING_ADDR_0_REGISTER 0x90 #define MEMORY_ENDING_ADDR_4_REGISTER 0x94 #define ENABLE_BANK_REGISTER 0xa0 #define AND_OR_EAGLE_REGISTER_USHORT(EAGLE_REGISTER, AND_MASK, OR_MASK) \ READ_EAGLE_REGISTER_USHORT(EAGLE_REGISTER) ;\ andi. r.3, r.3, AND_MASK ;\ ori r.3, r.3, OR_MASK ;\ WRITE_EAGLE_REGISTER_USHORT(EAGLE_REGISTER, r.3) #define WRITE_EAGLE_REGISTER_UCHAR(EAGLE_REGISTER, Register) \ LWI (r.23, EAGLE_ADDR_REG) ;\ LWI (r.24, 0x80000000 + EAGLE_REGISTER) ;\ rlwinm r.3, r.24, 0, 3 ;\ rlwinm r.24, r.24, 0, ~3 ;\ stwbrx r.24, 0, r.23 ;\ sync ;\ LWI (r.23, EAGLE_DATA_REG) ;\ stbx Register, r.3, r.23 ;\ sync #define WRITE_EAGLE_REGISTER_ULONG(EAGLE_REGISTER, Register) \ LWI (r.23, EAGLE_ADDR_REG) ;\ LWI (r.24, 0x80000000 + EAGLE_REGISTER) ;\ stwbrx r.24, 0, r.23 ;\ sync ;\ LWI (r.23, EAGLE_DATA_REG) ;\ stwbrx Register, 0, r.23 ;\ sync #define AND_OR_EAGLE_REGISTER_ULONG(EAGLE_REGISTER, AND_MASK, OR_MASK) \ READ_EAGLE_REGISTER_ULONG(EAGLE_REGISTER) ;\ LWI( r.23, AND_MASK) ;\ and r.3, r.3, r.23 ;\ LWI(r.23, OR_MASK) ;\ or r.3, r.3, r.23 ;\ WRITE_EAGLE_REGISTER_ULONG(EAGLE_REGISTER, r.3) //------------------------------------------------------------------------ // Macro: // MoveToRam // // Copy ROM to RAM at the destination specified by INIT_RAM_LOCATION. // After the copy is complete, begin executing from RAM at the new location // of MoveROMtoRAM@2. //------------------------------------------------------------------------ #define MoveToRam \ LWI (r.3, SYSTEM_ROM_PHYSICAL_BASE) ;\ LWI (r.4, INIT_RAM_LOCATION) ;\ LWI (r.5, ROM_SIZE) ;\ bl ..FwCopyMemory ;\ bl MoveROMtoRAM@1 ;\ MoveROMtoRAM@1: ;\ mflr r.3 ;\ rlwinm r.3, r.3, 0, 0x000fffff ;\ LWI (r.4, INIT_RAM_LOCATION) ;\ or r.3, r.3, r.4 ;\ addi r.3, r.3, MoveROMtoRAM@2 - MoveROMtoRAM@1 ;\ mtctr r.3 ;\ bctr ;\ MoveROMtoRAM@2: //------------------------------------------------------------------------ // Macro: // FwInitExcTableAndCodeSpace // // Zero the following address ranges: // 0 to EXCEPTION_TABLE_SIZE // ..FWstart to 8Meg //------------------------------------------------------------------------ #define FwInitExcTableAndCodeSpace\ xor r.3,r.3,r.3 ;\ addis r.4,0,0 ;\ addi r.4,r.4,EXCEPTION_TABLE_SIZE;\ bl ..FwTestAndZeroMemory ;\ bl FwInitExcTable ;\ .little_endian ;\ .long ..FWstart ;\ .big_endian ;\ FwInitExcTable: ;\ mflr r.3 ;\ lwbrx r.3,0,r.3 ;\ FwVirtualToPhysical(r.3) ;\ addis r.4,0,0x80 ;\ addi r.4,r.4,0 ;\ bl ..FwTestAndZeroMemory //------------------------------------------------------------------------ // Macro: // FwShadowFirmware // // Copy ROM image to the final destination in RAM. //------------------------------------------------------------------------ #define FwShadowFirmware \ bl FwShadowFirmware@1 ;\ FwShadowFirmware@1: ;\ mflr r.1 ;\ subi r.1,r.1,FwShadowFirmware@1 - ..FWstart ;\ mr r.3,r.1 ;\ bl FwShadowFirmware@2 ;\ .little_endian ;\ .long ..FWstart ;\ .big_endian ;\ FwShadowFirmware@2: ;\ mflr r.4 ;\ lwbrx r.4,0,r.4 ;\ FwVirtualToPhysical(r.4) ;\ LWI (r.5,ROM_SIZE) ;\ bl ..FwCopyMemory //LWI (r.5, (..FWstartend - ..FWstart)) ;\ //bl ..FwMoveMemory //------------------------------------------------------------------------ // Macro: // FwMungeMemory // // Little endian data (and code) from ROM requires munging and byte swapping // for use in PowerPC munged RAM. // //------------------------------------------------------------------------ #define FwMungeMemory \ bl FwMungeMemory@1 ;\ .little_endian ;\ .long ..FWstart ;\ .big_endian ;\ FwMungeMemory@1: ;\ mflr r.4 ;\ lwbrx r.4,0,r.4 ;\ FwVirtualToPhysical(r.4) ;\ mr r.3,r.4 ;\ LWI (r.5,ROM_SIZE) ;\ bl ..FwMungeAndByteSwap //------------------------------------------------------------------------ // Macro: // FwSetupTOC //------------------------------------------------------------------------ #define FwSetupTOC \ bl GetTOC ;\ .little_endian ;\ .long .toc ;\ .big_endian ;\ GetTOC: ;\ mflr r.2 ;\ lwbrx r.2, 0, r.2 //------------------------------------------------------------------------ // Macro: // FwInitExceptionVectorTable // // Copy exception table from linked location in RAM to physical zero. // Note: The RAM image was previously munged and byte swapped. //------------------------------------------------------------------------ #define FwInitExceptionVectorTable \ bl FwInitExceptionVectorTable@2 ;\ .little_endian ;\ .long ExceptionVectors ;\ .big_endian ;\ FwInitExceptionVectorTable@2: ;\ mflr r3 ;\ lwbrx r3,0,r3 ;\ FwVirtualToPhysical(r3) ;\ addi r4,0,0 ;\ addi r5,0,EXCEPTION_TABLE_SIZE ...
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