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Revision O
Published 06/99
DSP56364UM/D
DSP56364
24-Bit Digital Signal Processor
User’s Manual
Motorola, Incorporated
Semiconductor Products Sector
6501 William Cannon Drive West
Austin TX 78735-8598
This document (and other documents) can be viewed on the World Wide
Web at http://www.motorola-dsp.com.
This manual is one of a set of three documents. You need the following
additional manuals to have complete product information:
DSP56300 Family Manual
DSP56364 Technical Data
OnCE™ is a trademark of Motorola, Inc.
© MOTOROLA, INC., 1999
DSP56300FM/D
DSP56364/D
Rev. O; published 06/99
Order this document by
DSP56364UM/D
Motorola reserves the right to make changes without further notice to any products herein to improve
reliability, function, or design. Motorola does not assume any liability arising out of the application or use of
any product or circuit described herein; neither does it convey any license under its patent rights nor the
rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other application in which the failure of the Motorola
product could create a situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims,
costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim
of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges
that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer
TABLE OF CONTENTS
Paragraph
Number
Title
Page
Number
Preface ........................................................................................................................................... xi
Section 1
DSP56364 OVERVIEW
1.1
1.2
1.3
1.4
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.6
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.7
1.8
Introduction .......................................................................................................1-1
Features ............................................................................................................1-2
Audio Prodessor Architecture ...........................................................................1-4
Core Description ...............................................................................................1-4
DSP56300 Core Functional Blocks ...................................................................1-5
Data ALU ......................................................................................................1-5
Address Generation Unit (AGU) ...................................................................1-6
Program Control Unit (PCU) ........................................................................1-6
Internal Buses ..............................................................................................1-7
Direct Memory Access (DMA) ......................................................................1-8
PLL-based Clock Oscillator ..........................................................................1-8
JTAG TAP and OnCE Module .....................................................................1-9
Data and Program memory ...............................................................................1-9
Reserved Memory Spaces ...........................................................................1-9
Program ROM Area Reserved for Motorola Use .......................................1-10
Bootstrap ROM ..........................................................................................1-10
Dynamic Memory Configuration Switching ................................................1-10
External Memory Support ..........................................................................1-11
Internal I/O Memory Map ................................................................................1-11
Status Register (SR) .......................................................................................1-11
Section 2
Signal/Connection Descriptions
2.1
2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.5.3
2.6
Signal Groupings ...............................................................................................2-1
Power ................................................................................................................2-3
Ground ..............................................................................................................2-4
Clock and PLL ...................................................................................................2-5
External Memory Expansion Port (Port A) ........................................................2-6
External Address Bus ...................................................................................2-6
External Data Bus ........................................................................................2-6
External Bus Control ....................................................................................2-7
Interrupt and Mode Control ...............................................................................2-8
MOTOROLA
DSP56364 User’s Manual
iii
TABLE OF CONTENTS (Continued)
Paragraph
Number
2.7
2.8
2.9
2.10
Title
Page
Number
Serial Host Interface .........................................................................................2-9
Enhanced Serial Audio Interface ...................................................................2-12
JTAG/OnCE Interface .....................................................................................2-17
GPIO Signals ..................................................................................................2-17
Section 3
Memory Configuration
3.1
3.1.1
3.1.2
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
3.5
3.6
Memory Spaces ................................................................................................3-1
Program Memory Space ..............................................................................3-1
Data Memory Spaces ..................................................................................3-2
Memory Space Configuration ...........................................................................3-3
Internal Memory Configuration ..........................................................................3-4
RAM Locations .............................................................................................3-4
ROM Locations ............................................................................................3-5
Dynamic Memory Configuration Switching ..................................................3-5
Memory Maps ...................................................................................................3-7
External Memory Support .................................................................................3-9
Internal I/O Memory Map ..................................................................................3-9
Section 4
Core Configuration
4.1
4.2
4.2.1
4.2.2
4.2.3
4.3
4.4
4.5
4.6
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.8
4.9
4.10
Introduction .......................................................................................................4-1
Operating Mode Register (OMR) ......................................................................4-1
Mode C (MC) - Bit 2 .....................................................................................4-2
Address Attribute Priority Disable (APD) - Bit 14 .........................................4-2
Address Tracing Enable (ATE) - Bit 15 ........................................................4-2
Operating Modes ..............................................................................................4-3
Bootstrap Program ............................................................................................4-4
Interrupt Priority Registers ................................................................................4-5
DMA Request Sources .....................................................................................4-7
PLL and Clock Generator .................................................................................4-8
PLL Multiplication Factor (MF0-MF11) - Bits 0-11 .......................................4-8
Crystal Range Bit (XTLR) - Bit 15 ................................................................4-8
XTAL Disable Bit (XTLD) - Bit 16 .................................................................4-8
Clock Output Disable Bit (COD) - Bit 19 ......................................................4-8
PLL Pre-Divider Factor (PD0-PD3) - Bits 20-23 ..........................................4-8
Device Identification (ID) Register ....................................................................4-8
JTAG Identification (ID) Register ......................................................................4-9
JTAG Boundary Scan Register (BSR) ..............................................................4-9
iv
DSP56364 User’s Manual
MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph
Number
Title
Section 5
General Purpose Input/Output Port (GPIO)
5.1
5.2
5.2.1
5.2.2
Introduction .......................................................................................................5-1
GPIO Programming Model ................................................................................5-1
Port B Control Register (PCRB) ...................................................................5-2
Port B GPIO Data Register (PDRB) .............................................................5-3
Section 6
Enhanced Serial Audio Interface (ESAI)
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.2.12
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.4
6.4.1
6.4.2
6.4.3
Introduction .......................................................................................................6-1
ESAI Data and Control Pins ..............................................................................6-1
Serial Transmit Data Pin (SDO0) .................................................................6-1
Serial Transmit Data Pin (SDO1) .................................................................6-3
Serial Transmit/Receive Data Pin (SDO2/SDI3) ..........................................6-3
Serial Transmit/Receive Data Pin (SDO3/SDI2) ..........................................6-3
Serial Transmit/Receive Data Pin (SDO4/SDI1) ..........................................6-3
Serial Transmit/Receive Data Pin (SDO5/SDI0) ..........................................6-4
Receiver Serial Clock (SCKR) .....................................................................6-4
Transmitter Serial Clock (SCKT) ..................................................................6-4
Frame Sync for Receiver (FSR) ...................................................................6-5
Frame Sync for Transmitter (FST) ...............................................................6-6
High Frequency Clock for Transmitter (HCKT) ............................................6-7
High Frequency Clock for Receiver (HCKR) ................................................6-7
ESAI Programming Model .................................................................................6-7
ESAI Transmitter Clock Control Register (TCCR) .....................................6-11
ESAI Transmit Control Register (TCR) ......................................................6-14
ESAI Receive Clock Control Register (RCCR) ..........................................6-25
ESAI Receive Control Register (RCR) .......................................................6-28
ESAI Common Control Register (SAICR) ..................................................6-32
ESAI Status Register (SAISR) ...................................................................6-34
ESAI Receive Shift Registers .....................................................................6-37
ESAI Receive Data Registers (RX3, RX2, RX1, RX0) ...............................6-37
ESAI Transmit Shift Registers ....................................................................6-40
ESAI Transmit Data Registers (TX5, TX4, TX3, TX2, TX1,TX0) ...............6-40
ESAI Time Slot Register (TSR) ..................................................................6-40
Transmit Slot Mask Registers (TSMA, TSMB) ...........................................6-40
Receive Slot Mask Registers (RSMA, RSMB) ...........................................6-41
Operating Modes .............................................................................................6-41
ESAI after Reset ........................................................................................6-41
ESAI Initialization .......................................................................................6-42
ESAI Interrupt Requests ............................................................................6-42
Page
Number
MOTOROLA
DSP56364 User’s Manual
v

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