lcdtiming.pdf

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10/23/98
MC68328 Timing Amendment
DragonBall LCD Controller Timing
1
LFLM
LLP
2
LD[3:0]
3
4
LCLK
5
3.3V
NUM
1
2
3
4
5
CHARACTERISTIC
MINIMUM
Line Pulse to Frame Signal
Line Pulse Width
LCD Data Setup
LCD Data Hold
Shift Clock to Line Pulse
20
300
20
20
50
MAXIMUM
—
—
—
—
—
ns
ns
ns
ns
ns
UNIT
NOTE: This table contains the assumed active high logic for LFLM, LLP, and LCLK. The active edge is
alternated if the polarity of the corresponding signal is modified.
MOTOROLA
MC68328 Timing Amendment
-1

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