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MC68331
User’s Manual
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability
of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and
all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including
"Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others.
Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer
purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
MOTOROLA and
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
© MOTOROLA, INC. 1996
TABLE OF CONTENTS
Paragraph
Title
Page
SECTION 1INTRODUCTION
SECTION 2NOMENCLATURE
2.1
2.2
2.3
2.4
2.5
Symbols and Operators .................................................................................. 2-1
CPU32 Registers ............................................................................................ 2-2
Pin and Signal Mnemonics ............................................................................. 2-3
Register Mnemonics ....................................................................................... 2-5
Conventions ................................................................................................... 2-6
SECTION 3OVERVIEW
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.7
3.7.1
3.7.2
MCU Features ................................................................................................ 3-1
System Integration Module (SIM) ........................................................... 3-1
Central Processing Unit (CPU32) ........................................................... 3-1
Queued Serial Module (QSM) ................................................................ 3-1
General-Purpose Timer (GPT) ............................................................... 3-2
System Block Diagram and Pin Assignment Diagrams .................................. 3-2
Pin Descriptions ............................................................................................. 3-5
Signal Descriptions ......................................................................................... 3-7
Intermodule Bus ........................................................................................... 3-10
System Memory Map ................................................................................... 3-10
Internal Register Map ........................................................................... 3-10
Address Space Maps ........................................................................... 3-10
System Reset ............................................................................................... 3-16
SIM Reset Mode Selection ................................................................... 3-16
MCU Module Pin Function During Reset ............................................. 3-17
SECTION 4 SYSTEM INTEGRATION MODULE
4.1
General ........................................................................................................... 4-1
4.2
System Configuration and Protection ............................................................. 4-2
4.2.1
Module Mapping ..................................................................................... 4-3
4.2.2
Interrupt Arbitration ................................................................................. 4-3
4.2.3
Show Internal Cycles .............................................................................. 4-4
4.2.4
Factory Test Mode ................................................................................. 4-4
4.2.5
Register Access ..................................................................................... 4-4
4.2.6
Reset Status ........................................................................................... 4-4
4.2.7
Bus Monitor ............................................................................................ 4-4
4.2.8
Halt Monitor ............................................................................................ 4-5
4.2.9
Spurious Interrupt Monitor ...................................................................... 4-5
4.2.10
Software Watchdog ................................................................................ 4-5
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TABLE OF CONTENTS
Paragraph
(Continued)
Title
Page
4.2.11
Periodic Interrupt Timer .......................................................................... 4-7
4.2.12
Low-Power STOP Operation .................................................................. 4-8
4.2.13
Freeze Operation ................................................................................... 4-9
4.3
System Clock ................................................................................................. 4-9
4.3.1
Clock Sources ...................................................................................... 4-10
4.3.2
Clock Synthesizer Operation ................................................................ 4-10
4.3.3
External Bus Clock ............................................................................... 4-15
4.3.4
Low-Power Operation ........................................................................... 4-15
4.3.5
Loss of Reference Signal ..................................................................... 4-16
4.4
External Bus Interface .................................................................................. 4-17
4.4.1
Bus Signals .......................................................................................... 4-18
4.4.1.1
Address Bus ................................................................................. 4-18
4.4.1.2
Address Strobe ............................................................................ 4-18
4.4.1.3
Data Bus ...................................................................................... 4-18
4.4.1.4
Data Strobe .................................................................................. 4-18
4.4.1.5
Read/Write Signal ........................................................................ 4-18
4.4.1.6
Size Signals ................................................................................. 4-18
4.4.1.7
Function Codes ............................................................................ 4-19
4.4.1.8
Data and Size Acknowledge Signals ........................................... 4-19
4.4.1.9
Bus Error Signal ........................................................................... 4-19
4.4.1.10
Halt Signal .................................................................................... 4-20
4.4.1.11
Autovector Signal ......................................................................... 4-20
4.4.2
Dynamic Bus Sizing ............................................................................. 4-20
4.4.3
Operand Alignment .............................................................................. 4-21
4.4.4
Misaligned Operands ........................................................................... 4-21
4.4.5
Operand Transfer Cases ...................................................................... 4-22
4.5
Bus Operation .............................................................................................. 4-22
4.5.1
Synchronization to CLKOUT ................................................................ 4-23
4.5.2
Regular Bus Cycles .............................................................................. 4-23
4.5.2.1
Read Cycle ................................................................................... 4-24
4.5.2.2
Write Cycle ................................................................................... 4-25
4.5.3
Fast Termination Cycles ....................................................................... 4-25
4.5.4
CPU Space Cycles ............................................................................... 4-26
4.5.4.1
Breakpoint Acknowledge Cycle .................................................... 4-27
4.5.4.2
LPSTOP Broadcast Cycle ............................................................ 4-30
4.5.5
Bus Exception Control Cycles .............................................................. 4-30
4.5.5.1
Bus Errors .................................................................................... 4-32
4.5.5.2
Double Bus Faults ........................................................................ 4-32
4.5.5.3
Retry Operation ............................................................................ 4-33
4.5.5.4
Halt Operation .............................................................................. 4-33
4.5.6
External Bus Arbitration ........................................................................ 4-34
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Paragraph
4.5.6.1
4.5.6.2
4.6
4.6.1
4.6.2
4.6.3
4.6.3.1
4.6.3.2
4.6.3.3
4.6.4
4.6.5
4.6.5.1
4.6.5.2
4.6.6
4.6.7
4.6.8
4.6.9
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.8
4.8.1
4.8.1.1
4.8.1.2
4.8.1.3
4.8.1.4
4.8.2
4.8.3
4.8.4
4.9
4.9.1
4.9.2
4.9.3
4.10
(Continued)
Title
Page
Slave (Factory Test) Mode Arbitration ......................................... 4-35
Show Cycles ................................................................................ 4-35
Reset ............................................................................................................ 4-36
Reset Exception Processing ................................................................ 4-36
Reset Control Logic .............................................................................. 4-37
Reset Mode Selection .......................................................................... 4-37
Data Bus Mode Selection ............................................................. 4-38
Clock Mode Selection .................................................................. 4-40
Breakpoint Mode Selection .......................................................... 4-40
MCU Module Pin Function During Reset ............................................. 4-40
Pin State During Reset ......................................................................... 4-41
Reset States of SIM Pins ............................................................. 4-41
Reset States of Pins Assigned to Other MCU Modules ............... 4-42
Reset Timing ........................................................................................ 4-42
Power-On Reset ................................................................................... 4-43
Reset Processing Summary ................................................................. 4-44
Reset Status Register .......................................................................... 4-45
Interrupts ...................................................................................................... 4-45
Interrupt Exception Processing ............................................................ 4-45
Interrupt Priority and Recognition ......................................................... 4-45
Interrupt Acknowledge and Arbitration ................................................. 4-46
Interrupt Processing Summary ............................................................. 4-47
Interrupt Acknowledge Bus Cycles ....................................................... 4-48
Chip Selects ................................................................................................. 4-48
Chip-Select Registers ........................................................................... 4-50
Chip-Select Pin Assignment Registers ........................................ 4-51
Chip-Select Base Address Registers ........................................... 4-52
Chip-Select Option Registers ....................................................... 4-52
PORTC Data Register .................................................................. 4-54
Chip-Select Operation .......................................................................... 4-54
Using Chip-Select Signals for Interrupt Acknowledge .......................... 4-54
Chip-Select Reset Operation ................................................................ 4-55
Parallel Input/Output Ports ........................................................................... 4-57
Pin Assignment Registers .................................................................... 4-57
Data Direction Registers ...................................................................... 4-57
Data Registers ...................................................................................... 4-57
Factory Test ................................................................................................. 4-57
SECTION 5 CENTRAL PROCESSING UNIT
5.1
5.2
General ........................................................................................................... 5-1
CPU32 Registers ............................................................................................ 5-2
MOTOROLA
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MC68331
USER’S MANUAL

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