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MPR601UM-01
MPC601UM/AD
PowerPC 601
™
RISC Microprocessor User's Manual
CONTENTS
Paragraph
Number
Title
Page
Number
About This Book
Audience .............................................................................................................. xlii
Organization......................................................................................................... xlii
Additional Reading ............................................................................................. xliv
Conventions ........................................................................................................ xliv
Acronyms and Abbreviations ............................................................................. xliv
Terminology Conventions ................................................................................. xlvii
Chapter 1
Overview
1.1
1.1.1
1.1.2
1.1.3
1.1.3.1
1.1.4
1.1.4.1
1.1.4.2
1.1.4.3
1.1.5
1.1.6
1.1.7
1.1.8
1.2
1.3
1.3.1
1.3.2
1.3.2.1
1.3.2.1.1
1.3.2.1.2
1.3.2.1.3
1.3.2.1.4
1.3.2.1.5
PowerPC 601 Microprocessor Overview............................................................. 1-1
601 Features..................................................................................................... 1-2
Block Diagram................................................................................................. 1-3
Instruction Unit ................................................................................................ 1-5
Instruction Queue......................................................................................... 1-5
Independent Execution Units........................................................................... 1-5
Branch Processing Unit (BPU) .................................................................... 1-6
Integer Unit (IU) .......................................................................................... 1-6
Floating-Point Unit (FPU) ........................................................................... 1-7
Memory Management Unit (MMU) ................................................................ 1-7
Cache Unit ....................................................................................................... 1-8
Memory Unit.................................................................................................... 1-8
System Interface ............................................................................................ 1-10
Levels of the PowerPC Architecture.................................................................. 1-10
The 601 as a PowerPC Implementation............................................................. 1-11
Features.......................................................................................................... 1-12
Registers and Programming Model ............................................................... 1-13
PowerPC Registers and Programming Model ........................................... 1-13
General-Purpose Registers (GPRs)........................................................ 1-13
Floating-Point Registers (FPRs) ............................................................ 1-14
Condition Register (CR) ........................................................................ 1-14
Floating-Point Status and Control Register (FPSCR) ........................... 1-14
Machine State Register (MSR).............................................................. 1-14
Contents
iii
CONTENTS
Paragraph
Number
1.3.2.1.6
1.3.2.1.7
1.3.2.1.8
1.3.2.1.9
1.3.2.2
1.3.3
1.3.3.1
1.3.3.1.1
1.3.3.1.2
1.3.3.2
1.3.4
1.3.4.1
1.3.4.2
1.3.5
1.3.5.1
1.3.5.2
1.3.6
1.3.6.1
1.3.6.2
1.3.7
1.3.8
1.3.8.1
1.3.8.2
1.3.8.3
1.3.8.4
1.3.8.5
Title
Page
Number
Segment Registers (SRs) ........................................................................1-14
Special-Purpose Registers (SPRs)..........................................................1-14
User-Level SPRs ....................................................................................1-14
Supervisor-Level SPRs ..........................................................................1-15
Additional Registers in the 601 ..................................................................1-16
Instruction Set and Addressing Modes...........................................................1-18
PowerPC Instruction Set and Addressing Modes.......................................1-18
PowerPC Instruction Set ........................................................................1-18
Calculating Effective Addresses ............................................................1-19
601 Instruction Set......................................................................................1-20
Cache Implementation....................................................................................1-20
PowerPC Cache Characteristics .................................................................1-21
601 Cache Implementation.........................................................................1-21
Exception Model ............................................................................................1-22
PowerPC Exception Model ........................................................................1-23
The 601 Exception Model ..........................................................................1-24
Memory Management ....................................................................................1-27
PowerPC Memory Management ................................................................1-27
601 Memory Management .........................................................................1-28
601 Instruction Timing ...................................................................................1-29
System Interface .............................................................................................1-31
Memory Accesses.......................................................................................1-32
I/O Controller Interface Operations ...........................................................1-33
601 Signals .................................................................................................1-33
Signal Configuration ..................................................................................1-34
Real-Time Clock ........................................................................................1-35
Chapter 2
Registers and Data Types
2.1
2.1.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.4.1
2.2.4.2
2.2.4.3
2.2.5
2.2.5.1
Normal Instruction Execution State .....................................................................2-1
Changing Privilege Levels ...............................................................................2-6
User-Level Registers ............................................................................................2-6
General Purpose Registers (GPRs)...................................................................2-6
Floating-Point Registers (FPRs).......................................................................2-7
Floating-Point Status and Control Register (FPSCR) ......................................2-8
Condition Register (CR).................................................................................2-11
Condition Register CR0 Field Definition...................................................2-12
Condition Register CR1 Field Definition...................................................2-12
Condition Register CR
n
Field—Compare Instruction ...............................2-12
User-Level SPRs ............................................................................................2-13
MQ Register (MQ) .....................................................................................2-13
iv
PowerPC 601 RISC Microprocessor User's Manual
CONTENTS
2.2.5.2
2.2.5.3
2.2.5.3.1
2.2.5.3.2
2.2.5.3.3
2.2.5.3.4
2.2.5.4
2.2.5.5
2.3
2.3.1
2.3.2
2.3.3
2.3.3.1
2.3.3.1.1
2.3.3.1.2
2.3.3.2
2.3.3.3
2.3.3.4
2.3.3.5
2.3.3.5.1
2.3.3.5.2
2.3.3.6
2.3.3.7
2.3.3.8
2.3.3.9
2.3.3.10
2.3.3.11
2.3.3.12
2.3.3.13
2.3.3.13.1
2.3.3.13.2
2.3.3.13.3
2.3.3.13.4
2.3.3.13.5
2.4
2.4.1
2.4.1.1
2.4.2
2.4.2.1
2.4.2.2
2.4.2.3
2.4.3
2.4.3.1
Integer Exception Register (XER) .............................................................2-15
Real-Time Clock (RTC) Registers (User-Level) .......................................2-16
Real-Time Clock Lower (RTCL) Register ............................................2-17
Real-Time Clock Upper (RTCU) Register ............................................2-18
Reading the RTC....................................................................................2-18
RTC Synchronization in a Multiprocessor System................................2-19
Link Register (LR) .....................................................................................2-19
Count Register (CTR) ................................................................................2-20
Supervisor-Level Registers ................................................................................2-20
Machine State Register (MSR) ......................................................................2-20
Segment Registers..........................................................................................2-22
Supervisor-Level SPRs ..................................................................................2-24
Synchronization for Supervisor-Level SPRs and Segment Registers........2-25
Context Synchronization........................................................................2-25
Other Synchronization Requirements by Register.................................2-29
DAE/Source Instruction Service Register (DSISR)...................................2-29
Data Address Register (DAR)....................................................................2-30
Real-Time Clock (RTC) Registers (Supervisor-Level) .............................2-30
Decrementer (DEC) Register .....................................................................2-30
Decrementer Operation ..........................................................................2-31
Writing and Reading the DEC ...............................................................2-31
Table Search Description Register 1 (SDR1) ............................................2-32
Machine Status Save/Restore Register 0 (SRR0) ......................................2-32
Machine Status Save/Restore Register 1 (SRR1) ......................................2-33
General SPRs (SPRG0–SPRG3)................................................................2-33
External Access Register (EAR)................................................................2-34
Processor Version Register (PVR).............................................................2-35
BAT Registers............................................................................................2-36
601 Implementation-Specific HID Registers .............................................2-38
Checkstop Sources and Enables Register—HID0 .................................2-38
601 Debug Modes Register—HID1.......................................................2-41
Instruction Address Breakpoint Register (IABR)—HID2.....................2-42
Data Address Breakpoint Register (DABR)—HID5 .............................2-42
Processor Identification Register (PIR)—HID15 ..................................2-44
Operand Conventions.........................................................................................2-44
Data Organization in Memory and Data Transfers ........................................2-44
Alignment and Misaligned Accesses .........................................................2-45
Effect of Operand Placement on Performance...............................................2-45
Instruction Restart ......................................................................................2-46
Atomicity ...................................................................................................2-47
Access Order ..............................................................................................2-47
Byte and Bit Ordering ....................................................................................2-47
Little-Endian Address Manipulation..........................................................2-48
Contents
v

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