MPC823SIU.pdf

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SIU Interrupt Controller
SIU Interrupt Controller
11 - 1
SIU Interrupts
SWT
IREQ[0:7]
NMI
GEN
IRQ 0
NMI
DEC
S
I
U
I
N
T
C
N
T
R
L
R
Edge/
Level
Level 7
Level 6
Level5
Level 4
Level 3
DEC
TB
PIT
RTC
PCMCIA
EPPC
CORE
IREQ
• SIU Receives an interrupt
from 1 of 8 external sources or 1
of 8 internal sources
– Assuming no masking
• SIU asserts the IREQ input to
the EPPC Core
Level 2
Level 1
Level 0
DEBUG
DEBUG
System Interface Unit (SIU)
PORT C[ :15]
4
TIMER1
TIMER2
TIMER3
TIMER4
SCC1
SCC2
SMC1
C
P
M
I
N
T
C
N
T
R
L
R
To SIU Interrupt Controller
Communication
SMC2
Processor
SPI
Module
(CPM)
I
2
C
PIP
IDMA1
IDMA2
SDMA
RISC TIMERS
• CPIC Generates an interrupt to the SIU Interrupt
Controller at a User Programmable Level
SIU Interrupt Controller
11 - 2
Flow Diagram: How SIU Processes an Interrupts
Start
SIU Interrupt occurs
Set bit in SIPEND
Bit set in
SIMASK ?
N
END
Y
To IREQ of EPPC
SIU Interrupt Controller
11 - 3
Vector Table
VECTOR
OFFSET
(HEX)
0 0000
0 0100
0 0200
0 0300
0 0400
0 0500
0 0600
0 0700
0 0800
0 0900
0 0A00
0 0B00
0 0C00
0 0D00
0 0E00
0 1000
0 1100
0 1200
0 1300
0 1400
0 1500 -
01BFF
0 1C00
0 1D00
0 1E00
0 1F00
EXCEPTION TYPE
RESERVED
SYSTEM RESET
MACHINE CHECK
DATA STORAGE
INSTRUCTION STORAGE
EXTERNAL INTERRUPT
ALIGNMENT
PROGRAM
FLOATING-POINT UNAVAILABLE
DECREMENTER
RESERVED
RESERVED
SYSTEM CALL
TRACE*
FLOATING-POINT ASSIST*
IMPLEMENTATION DEPENDENT SOFTWARE EMULATION
IMPLEMENTATION DEPENDENT INSTRUCTION TLB MISS
IRQ[1 :7], PIT, TB, RTC, PCMCIA, CPM
HARD & SRESETS
TEA (BUS ERROR)
ALIGNMENT ERROR
INSTR. TRAPS,ERRORS, ILLEGAL,
PRIVILEGED
MSR[FP]=0 & F.P. INSTRUCTION
ENCOUNTERED
DECREMENTER REGISTER
'SC' INSTRUCTION
SINGLE-STEP OR BRANCH TRACING
SOFTWARE ASSIST FOR INFREQUENT &
COMPLEX FP OPERATIONS
IMPLEMENTATION DEPENDENT DATA TLB MISS
IMPLEMENTATION DEPENDENT INSTRUCTION TLB ERROR
IMPLEMENTATION DEPENDENT DATA TLB ERROR
RESERVED
IMPLEMENTATION DEPENDENT DATA BREAKPOINT
IMPLEMENTATION DEPENDENT INSTRUCTION BREAKPOINT
IMPLEMENTATION DEPENDENT PERIPHERAL BREAKPOINT
IMPLEMENTATION DEPENDENT NON MASKABLE DEVELOPMENT PORT
SIU Interrupt Controller
11 - 4
SIU Interrupt Sources
SWT
IRQ[0:7]
EDGE
DET
DEC
TB
PIT
RTC
PCMCIA
CPM
int. controller
Level 7
Level 6
Level5
Level 4
Level 3
Level 2
Level 1
Level 0
DEBUG
NMI
GEN
IRQ0
NMI
DEC
S
I
U
I
N
T
C
N
T
R
L
R
EPPC
CORE
IREQ
DEBUG
SIU
System Configuration and Protection Logic
Module
Configuration
Bus
Monitor
TEA signal
Periodic Int
Timer
Software
Watchdog
Clock
PPC
Decrementer
PPC
Time Base
Real Time
Clock
SIU Interrupt Controller
interrupt
interrupt o
system rese
interrupt
interrupt
interrupt
11 - 5

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