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Overview
Programming Model
Cache and Bus Interface Unit Operation
Exceptions
Memory Management
Instruction Timing
Signal Descriptions
System Interface Operation
Performance Monitor
1
2
3
4
5
6
7
8
9
PowerPC Instruction Set Listings
Invalid Instruction Forms
PowerPC 604 Processor System Design
and Programming Considerations
A
B
C
Glossary
GLO
Index
IND
1
2
3
4
5
6
7
8
9
Overview
Programming Model
Cache and Bus Interface Unit Operation
Exceptions
Memory Management
Instruction Timing
Signal Descriptions
System Interface Operation
Performance Monitor
A
B
C
GLO
IND
PowerPC Instruction Set Listings
Invalid Instruction Forms
PowerPC 604 Processor System Design
and Programming Considerations
Glossary
Index
G522-0330-00
MPC604EUM/AD
3/98
PowerPC 604e
™
RISC Microprocessor User's Manual
with Supplement for PowerPC 604™ Microprocessor
.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or
implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this
document.
The PowerPC 604e microprocessor embodies the intellectual property of IBM and of Motorola. However, neither party assumes any responsibility or
liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party. Neither party is to be
considered an agent or representative of the other party, and neither has granted any right or authority to the other to assume or create any express or
implied obligations on its behalf. Information such as data sheets, as well as sales terms and conditions such as prices, schedules, and support, for the
microprocessor may vary as between IBM and Motorola. Accordingly, customers wishing to learn more information about the products as marketed by a
given party should contact that party.
Both IBM and Motorola reserve the right to modify this manual and/or any of the products as described herein without further notice. Nothing in this
manual, nor in any of the errata sheets, data sheets, and other supporting documentation, shall be interpreted as conveying an express or implied
warranty, representation, or guarantee regarding the suitability of the products for any particular purpose. The parties do not assume any liability or
obligation for damages of any kind arising out of the application or use of these materials. Any warranty or other obligations as to the products described
herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the marketing party and the customer.
In the absence of such an agreement, no liability is assumed by the marketing party for any damages, actual or otherwise.
“Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals,” must be validated for each customer
application by customer’s technical experts. Neither IBM nor Motorola convey any license under their respective intellectual property rights nor the rights
of others. The products described in this manual are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation
where personal injury or death may occur. Should customer purchase or use the products for any such unintended or unauthorized application, customer
shall indemnify and hold IBM and Motorola and their respective officers, employees, subsidiaries, affiliates, and distributors harmless against all claims,
costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with
such unintended or unauthorized use, even if such claim alleges that Motorola or IBM was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
The PowerPC name, the PowerPC logotype, PowerPC 601, PowerPC 603, PowerPC 603e, PowerPC 604, and PowerPC 604e are trademarks of
International Business Machines Corporation used by Motorola under license from International Business Machines Corporation.
© Motorola Inc. 1998. All rights reserved.
Portions hereof © International Business Machines Corp. 1991–1998. All rights reserved.
CONTENTS
Paragraph
Number
Title
Page
Number
About This Book
Audience ............................................................................................................ xxiv
Organization.........................................................................................................xxv
Suggested Reading............................................................................................. xxvi
General Information.......................................................................................... xxvi
PowerPC Documentation.................................................................................. xxvi
Conventions ..................................................................................................... xxviii
Acronyms and Abbreviations ............................................................................ xxix
Terminology Conventions ................................................................................ xxxii
Chapter 1
Overview
1.1
1.2
1.3
1.3.1
1.3.2
1.3.2.1
1.3.2.2
1.3.2.3
1.3.3
1.3.3.1
1.3.3.2
1.3.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.3.9
Overview.............................................................................................................. 1-1
PowerPC 604e Microprocessor Features ............................................................. 1-2
PowerPC Architecture Implementation ............................................................... 1-8
Features............................................................................................................ 1-9
PowerPC 604e Processor Programming Model............................................. 1-10
Implementation-Specific Registers............................................................ 1-10
Support for Misaligned Little-Endian Accesses ........................................ 1-12
Instruction Set ............................................................................................ 1-13
Cache and Bus Interface Unit Operation ....................................................... 1-14
Instruction Cache ....................................................................................... 1-14
Data Cache................................................................................................. 1-15
Additional Changes to the Cache .............................................................. 1-15
Exceptions...................................................................................................... 1-16
Memory Management.................................................................................... 1-21
Instruction Timing ......................................................................................... 1-21
Signal Descriptions ........................................................................................ 1-24
System Interface Operation .......................................................................... 1-27
Performance Monitor..................................................................................... 1-28
Chapter 2
Programming Model
2.1
2.1.1
2.1.2
2.1.2.1
2.1.2.2
2.1.2.3
Register Set .......................................................................................................... 2-1
Register Set ...................................................................................................... 2-2
PowerPC 604e-Specific Registers ................................................................... 2-8
Instruction Address Breakpoint Register (IABR)........................................ 2-9
Processor Identification Register (PIR) ....................................................... 2-9
Hardware Implementation-Dependent Register 0 ..................................... 2-10
Contents
v

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